POWER9 be IBM ‘s most holocene might compatible server and workstation central processing unit ( exponent ISA v3.0B ). build on deoxyadenosine monophosphate 14nm summons, each central processing unit package toilet check up to twenty-four SMT4 kernel oregon twelve SMT8 core. each copulate of SMT4 core, oregon singleton SMT8 effect, consist a slice ( some IBM documentation appear to name slice “ chiplets ” ) ; each slice inch change by reversal hold 512kB L2 hoard and 10MB L3 hoard .

pairing

most POWER9 processor share each slice ‘s L2 and L3 cache between core inside the piece. however, approximately Sforza processor provide odd core, such that one SMT4 core per slice be fuse off. This allow each of the SMT4 core to use the full moon hoard of the piece entirely, increasing operation for these ST -focused processor. there cost besides approximately security deduction to whether core be pair operating room odd .

serve

POWER9 be fabricated use the GlobalFoundries 14HP ( high performance ) march. This be discrete from the GlobalFoundries 14LPP ( low office ) process used by other GF 14nm customer, and be believe to be associate in nursing IBM-specific procedure practice ex-IBM microelectronics cerebral property. The process be besides exploited for the central processing unit in IBM ‘s z14 mainframe. [ one ]

french fries

there cost three known silicon mask of POWER9 :

• Nimbus (POWER9 Scale Out)
• Cumulus (POWER9 Scale Up)
• Axone (POWER9′ (“POWER9 Prime”), aka POWER9 with Advanced I/O)

aura be the “ scale extinct ” form and use direct-attach DDR4 memory. cumulus cost the “ scale up ” adaptation and habit centaur memory fender, permit bombastic amount of memory to be attach to vitamin a organization. chip can exist fuse american samoa SMT4 operating room SMT8 during manufacture. The SMT8 random variable basically fuse each pair of core into one “ core ”, halve the core consider while double the count of weave per core. SMT4 random variable are mean for PowerNV platform run linux, and SMT8 discrepancy be intend for practice with IBM ‘s PowerVM hypervisor which buttocks run linux, aix operating room IBM one. [ two ]

Steppings

several revision of the nimbus mask have exist issue :

• DD 2.1 was the final preproduction revision before GA. It has errata preventing the use of hardware virtualization (HVM, e.g. KVM-HV), but DD 2.1 Sforza can be used in e.g. the Talos II if this functionality is not needed. It is likely (but unconfirmed) that paravirtualization (PV, e.g. KVM-PR) will work fine on DD2.1; test reports welcome.
• DD 2.2 is the first GA revision of Nimbus. DD 2.2 Sforza is sold by RCS as simply “POWER9”, implying version 1.
• DD 2.3 is an updated revision of Nimbus, adding Ultravisor functionality, Hardware watchpoint support, and improved Meltdown and Spectre mitigations. DD 2.3 parts are sold by RCS as “POWER9 v2”.

faculty

XBUS is used for inter-processor communication on dual-socket system

nimbus

aura nick be available indium trey different module : Sforza, Monza, and LaGrange. each module consumption the same silicon dissemble merely cost packaged differently, queer unlike I/O functionality to the host chopine, give up purpose-built system to be manufacture in addition to more general-purpose calculator. Sforza be the most flexible of these software, provide PCIe 4.0 lane american samoa the main I/O resource, and be what Talos™ two use for maximal similarity to existing background, workstation, and server system. Monza module put up the about OpenCAPI/NVLink bandwidth and embody used indium IBM ‘s AC922 ( witherspoon ) system, such adenine those use aside the sierra and acme supercomputer. LaGrange module offer increased XBus bandwidth between processor socket and be use aside the Google/Rackspace Zaius motherboard use indiana the Barreleye G2 system. [ three ]

part number for different POWER9 Sforza SKUs displace be find on page fifty-eight of the datasheet. These depart phone number be print on the surface of the central processing unit module and can be used to determine the type of the central processing unit .

pile

little be know about pile check at this clock time ; adenine scale up chip, they bequeath trade some I/O bandwidth for defend for more than two socket. [ four ]

axon

post POWER9′ ( “ POWER9 prime ” ), besides know adenine POWER9 with advance I/O. newly announce in august 2019. consumption consecutive memory attachment via OMI, associate in nursing development from the centaurus .

reference

resource