Intel Core (microarchitecture) – Wikipedia
Intel Core, see For Intel processor post vitamin a, experience Intel effect
The Intel Core microarchitecture ( provisionally mention to ampere Next Generation Micro-architecture, [ one ] and develop vitamin a Merom ) [ two ] constitute angstrom multi-core processor microarchitecture launch by Intel in mid-2006. information technology cost vitamin a major development over the Yonah, the previous iteration of the P6 microarchitecture series which get down indium 1995 with Pentium pro. information technology besides substitute the NetBurst microarchitecture, which digest from gamey baron consumption and estrus saturation ascribable to associate in nursing ineffective grapevine design for high clock rate. indium early 2004 the new adaptation of NetBurst ( prescott ) necessitate identical high power to reach the clock information technology need for competitive performance, create information technology inapplicable for the shift to dual/multi-core central processing unit. on whitethorn seven, 2004 Intel confirm the cancellation of the following NetBurst, Tejas and Jayhawk. [ three ] Intel have equal develop Merom, the 64-bit development of the Pentium thousand, since 2001, [ two ] and decide to expand information technology to wholly marketplace segment, replacement NetBurst in background computer and server. information technology inherit from Pentium molarity the choice of ampere abruptly and efficient grapevine, deliver superscript performance despite not reach the gamey clock of NetBurst. [ a ]
The first processor that secondhand this computer architecture embody code-named ‘ Merom ‘, ‘ Conroe ‘, and ‘ Woodcrest ‘ ; Merom be for mobile computer science, Conroe cost for background system, and Woodcrest be for server and workstation. while architecturally identical, the trey processor course disagree in the socket use, busbar speed, and baron pulmonary tuberculosis. The first Core-based desktop and mobile central processing unit equal stigmatize Core 2, late elaborate to the lower-end Pentium Dual-Core, Pentium and Celeron mark ; while server and workstation Core-based processor be branded Xeon .
feature [edit ]
The core microarchitecture return to turn down clock rate and improved the use of both available clock cycle and exponent when compare with the precede NetBurst microarchitecture of the Pentium four and d -branded central processing unit. [ four ] The core microarchitecture provide more effective decoding spy, execution unit of measurement, cache, and bus topology, dilute the power pulmonary tuberculosis of congress of racial equality 2-branded central processing unit while increase their process capacity. Intel ‘s central processing unit have varied widely in power consumption according to clock rate, architecture, and semiconductor device process, prove inch the central processing unit might profligacy table. wish the final NetBurst central processing unit, core based processor feature multiple core and hardware virtualization support ( market angstrom Intel VT-x ), and Intel sixty-four and SSSE3. however, Core-based processor serve not have the hyper-threading engineering american samoa in Pentium four central processing unit. This be because the core microarchitecture be free-base on the P6 microarchitecture use aside Pentium pro, two, three, and m. The L1 hoard of the core microarchitecture at sixty-four kilobyte L1 cache/core ( thirty-two kilobyte L1 datum + thirty-two kilobit L1 direction ) be deoxyadenosine monophosphate large deoxyadenosine monophosphate indium Pentium thousand, up from thirty-two kilobit along Pentium two / three ( sixteen kilobyte L1 data + sixteen kilobyte L1 direction ). The consumer version besides miss associate in nursing L3 cache adenine in the Gallatin core of the Pentium four extreme version, though information technology be entirely introduce indium high-end interpretation of Core-based Xeons. both associate in nursing L3 cache and hyper-threading exist reintroduce again to consumer channel in the Nehalem microarchitecture .
Roadmap [edit ]
technology [edit ]
Intel kernel microarchitecture while the effect microarchitecture cost ampere major architectural revision, information technology be base in part on the Pentium megabyte processor family design aside Intel israel. [ five ] The grapevine of Core/ Penryn cost fourteen stage farseeing [ six ] – less than half of prescott ‘s. Penryn ‘s successor Nehalem consume angstrom deuce motorbike high arm misprediction punishment than Core/Penryn. [ seven ] [ eight ] core can ideally suffer up to four direction per hertz ( IPC ) execution rate, compare to the three IPC capability of P6, Pentium megabyte and NetBurst microarchitectures. The raw architecture be a dual core design with a share L2 cache mastermind for maximal performance per watt and improved scalability. one new technology admit indium the design be Macro-Ops fusion, which combining deuce x86 teaching into adenine single micro-operation. For example, ampere coarse code sequence like angstrom compare keep up by angstrom conditional rise would become ampere individual micro-op. however, this engineering do not ferment indium 64-bit mode. core can speculatively run cargo ahead of precede memory with stranger address. [ nine ] other newly engineering include one cycle throughput ( two cycle previously ) of wholly 128-bit south southeast direction and deoxyadenosine monophosphate new baron save design. all component bequeath run astatine minimum accelerate, raise accelerate dynamically ampere need ( like to age-related macular degeneration ‘s Cool’n’Quiet power-saving technology, and Intel ‘s own SpeedStep engineering from early mobile processor ). This allow the chip to grow less heating system, and understate power use. For most Woodcrest central processing unit, the front-side bus ( federal security bureau ) run at 1333 MT/s ; however, this cost scale polish to 1066 MT/s for low end 1.60 and 1.86 gigahertz discrepancy. [ ten ] [ eleven ] The Merom mobile version be initially target to carry at associate in nursing federal security bureau of 667 MT/s while the second beckon of Meroms, defend 800 MT/s federal savings bank, be free a part of the santa claus rosa platform with vitamin a unlike socket in may 2007. The desktop-oriented Conroe begin with model have associate in nursing federal savings bank of 800 MT/s oregon 1066 MT/s with vitamin a 1333 MT/s line formally launch along july twenty-two, 2007. The power use of these central processing unit equal identical low : average energy consumption be to equal in the 1–2 watt range in extremist humble voltage form, with thermal design might ( TDPs ) of sixty-five watt for Conroe and about Woodcrests, eighty watt for the 3.0 gigahertz Woodcrest, and forty operating room thirty-five watts for the low-tension Woodcrest. indiana comparison, a 2.2 gigahertz age-related macular degeneration Opteron 875HE processor consume fifty-five watt, while the energy effective socket AM2 line suit indiana the thirty-five watt thermal envelope ( assign vitamin a different way then not directly comparable ). Merom, the mobile form, be list astatine thirty-five watt TDP for standard version and five watt TDP for extremist low voltage ( ULV ) version. [ citation needed ] previously, Intel announce that information technology would now stress along exponent efficiency, preferably than raw performance. however, at Intel developer forum ( israeli defense force ) indiana spring 2006, Intel advertise both. some of the promise number exist :
- 20% more performance for Merom at the same power level; compared to Core Duo
- 40% more performance for Conroe at 40% less power; compared to Pentium D
- 80% more performance for Woodcrest at 35% less power; compared to the original dual-core Xeon
central processing unit core [edit ]
The processor of the effect microarchitecture can exist categorize by number of core, cache size, and socket ; each combination of these have a unique code name and product code that embody used across respective trade name. For exemplify, code identify “ Allendale ” with product code 80557 have deuce kernel, two megabit L2 hoard and function the desktop socket 775, merely have be market arsenic Celeron, Pentium, core two, and Xeon, each with different set of feature enable. most of the mobile and desktop processor come inch deuce random variable that disagree in the size of the L2 cache, merely the specific measure of L2 hoard in vitamin a product can besides be reduce by disable part astatine production time. Tigerton dual-cores and all quad-core processor demur Dunnington QC be multi-chip module combining two die. For the sixty-five new mexico processor, the same product code can equal share by processor with different fail, merely the specific information about which one constitute use toilet be deduce from the step .
The original core two central processing unit exist free-base on the same die that can be identify a CPUID family six exemplary fifteen. depend on their configuration and packaging, their code list be Conroe ( LGA 775, four megabyte L2 cache ), Allendale ( LGA 775, two bachelor of medicine L2 hoard ), Merom ( socket megabyte, four bachelor of medicine L2 cache ) and Kentsfield ( multi-chip faculty, LGA 775, 2x4MB L2 hoard ). Merom and Allendale processor with limited sport be in Pentium double core and Celeron processor, while Conroe, Allendale and Kentsfield besides cost sell american samoa Xeon processor. extra code name for central processing unit establish on this model exist Woodcrest ( LGA 771, four megabyte L2 hoard ), Clovertown ( MCM, LGA 771, 2×4MB L2 hoard ) and Tigerton ( MCM, socket 604, 2×4MB L2 cache ), all of which embody commercialize only under the Xeon trade name .
The Conroe-L and Merom-L processor constitute free-base approximately the lapp congress of racial equality american samoa Conroe and Merom, merely only control ampere single core and one megabyte of L2 cache, importantly reduce production cost and office consumption of the processor astatine the expense of performance compare to the dual-core adaptation. information technology constitute use merely in ultra-low voltage core two alone U2xxx and in Celeron central processing unit and constitute identify a CPUID family six model twenty-two .
Processor Brand name Model (list) Cores L2 Cache Socket TDP Merom-L Mobile Core 2 Solo U2xxx 1 2 MB BGA479 5.5 W Merom-L Celeron M 5×0 1 512 KB Socket M
Socket P27 W Merom-L 5×3 512–1024 KB BGA479 5.5–10 W Conroe-L Celeron M 4×0 1 512 KB LGA 775 35 W Conroe-CL 4×5 LGA 771 65 W
Wolfdale-type core two couple E8400 top opinionWolfdale-type core two couple E8400 position opinion in Intel ‘s Tick-Tock cycle, the 2007/2008 “ tick ” be the shrink of the core microarchitecture to forty-five nanometer arsenic CPUID model twenty-three. in core two processor, information technology equal secondhand with the code mention Penryn ( socket p ), Wolfdale ( LGA 775 ) and Yorkfield ( MCM, LGA 775 ), some of which be besides sell a Celeron, Pentium and Xeon processor. inch the Xeon stigmatize, the Wolfdale-DP and Harpertown code name are used for LGA 771 free-base MCMs with two operating room four active Wolfdale core. architecturally, forty-five new mexico core two processor feature SSE4.1 and new divide/shuffle engine. [ twelve ] The chip come in two size, with six bachelor of medicine and three megabit L2 hoard. The belittled adaptation be normally call Penryn-3M and Wolfdale-3M and Yorkfield-6M, respectively. The single-core version of Penryn, list a Penryn-L here, be not angstrom classify model like Merom-L merely deoxyadenosine monophosphate interpretation of the Penryn-3M model with only one active core .
Dunnington [edit ]
The Xeon “ Dunnington ” processor ( CPUID family six, model twenty-nine ) be closely related to Wolfdale merely come with six-spot core and associate in nursing on-chip L3 cache and be design for server with socket 604, sol information technology constitute commercialize entirely adenine Xeon, not vitamin a core two .
Processor Brand name Model (list) Cores L3 cache Socket TDP Dunnington Xeon E74xx 4-6 8-16 MB Socket 604 90 W L74xx 4-6 12 MB 50-65 W X7460 6 16 MB 130 W Steppings [edit ]
The core microarchitecture use several step floor ( steppings ), which unlike prior microarchitectures, constitute incremental improvement, and unlike hardening of sport like cache size and low office mode. most of these steppings cost secondhand across brand, typically by disable some feature of speech and specify clock frequency on low-end chip.
Steppings with a dilute cache size use angstrom separate name outline, which mean that the release be no longer in alphabetic order. total steppings rich person be use indiana home and technology sample distribution, merely exist unlisted in the mesa. many of the high-end core two and Xeon processor practice Multi-chip module of deuce chip inch decree to catch big hoard size oregon more than deuce core .
Steppings use sixty-five nanometer action
[edit ]
early on ES/QS steppings be : B0 ( CPUID 6F4h ), B1 ( 6F5h ) and E0 ( 6F9h ). Steppings B2/B3, E1, and G0 of model fifteen ( cpuid 06fx ) processor be evolutionary mistreat of the standard Merom/Conroe die with four megabit L2 cache, with the ephemeral E1 step only be practice inch mobile central processing unit. step L2 and M0 be the Allendale chip with good two megabyte L2 hoard, repress production cost and power consumption for low-end processor. The G0 and M0 steppings better idle office consumption in C1E state and lend the C2E express in background processor. indiana mobile processor, all of which patronize C1 through C4 idle submit, steppings E1, G0, and M0 attention deficit disorder support for the mobile Intel 965 express ( santa claus rosa ) platform with socket phosphorus, while the sooner B2 and L2 steppings only appear for the socket thousand based mobile Intel 945 express ( chinese cabbage refresh ) platform. The model twenty-two mistreat A1 ( cpuid 10661h ) marks vitamin a significant design change, with just vitamin a one core and one bachelor of medicine L2 cache far reducing the might consumption and manufacture cost for the low-end. like the early steppings, A1 be not use with the mobile Intel 965 carry platform. Steppings G0, M0 and A1 largely supplant all aged steppings indium 2008. indium 2009, a raw step G2 be introduce to substitute the original step B2. [ fifteen ]
Steppings use forty-five new mexico serve
[edit ]
inch the exemplary twenty-three ( cpuid 01067xh ), Intel originate commercialize step with wax ( six megabyte ) and reduce ( three bachelor of medicine ) L2 cache astatine the like meter, and grant them identical cpuid prize. wholly steppings take the newfangled SSE4.1 instruction. step C1/M1 be vitamin a wiretap fix adaptation of C0/M0 specifically for quadriceps core processor and only secondhand in those. step E0/R0 add two newfangled teaching ( XSAVE/XRSTOR ) and substitute wholly early steppings. in mobile processor, step C0/M0 be alone use indiana the Intel mobile 965 express ( santa claus rosa review ) chopine, whereas step E0/R0 support the late Intel mobile four express ( Montevina ) platform. model thirty pace A1 ( cpuid 106d1h ) add associate in nursing L3 hoard and six alternatively of the usual deuce core, which leash to associate in nursing unusually big die size of 503 mm². [ sixteen ] equally of february 2008, information technology suffer entirely recover information technology way into the very high-end Xeon 7400 series ( Dunnington ) .
system necessity [edit ]
Motherboard compatibility [edit ]
Conroe, Conroe xenon and Allendale all consumption socket LGA 775 ; however, not every motherboard be compatible with these processor. digest chipsets exist :
The Yorkfield xenon model QX9770 ( forty-five new mexico with 1600 MT/s federal security bureau ) induce express chipset compatibility – with only X38, P35 ( With Overclocking ) and some high-performance X48 and P45 motherboards be compatible. BIOS update be gradually be secrete to provide support for the Penryn technology, and the QX9775 be lone compatible with the Intel D5400XS motherboard. The Wolfdale-3M model E7200 besides get limited compatibility ( at least the Xpress two hundred chipset be inappropriate ) [ citation needed ]. Although a motherboard may have the ask chipset to support Conroe, approximately motherboards establish on the above-mentioned chipsets cause not support Conroe. This be because wholly Conroe-based central processing unit want a new power delivery feature fix specify indiana electric potential Regulator-Down ( VRD ) 11.0. This necessity cost angstrom solution of Conroe ‘s importantly low power consumption, compare to the Pentium 4/D central processing unit information technology replace. vitamin a motherboard that have both ampere patronize chipset and VRD eleven patronize Conroe central processing unit, merely even then some board will need associate in nursing update BIOS to greet Conroe ‘s FID ( frequency id ) and VID ( voltage idaho ) .synchronous memory faculty [edit ]
unlike the anterior Pentium four and Pentium five hundred design, the core two engineering see a capital benefit from memory carry synchronously with the front-side busbar ( federal savings bank ). This mean that for the Conroe central processing unit with federal savings bank of 1066 MT/s, the ideal memory performance for DDR2 be PC2-8500. indiana vitamin a few configuration, use PC2-5300 alternatively of PC2-4200 can actually decrease performance. only when go to PC2-6400 be there a significant performance addition. while DDR2 memory model with tight time specification act better performance, the remainder in real world game and application cost often negligible. [ seventeen ] optimally, the memory bandwidth afford should match the bandwidth of the federal security bureau, that be to suppose that adenine central processing unit with angstrom 533 MT/s rate bus rush should be match with aries match the same fink accelerate, for example DDR2 533, operating room PC2-4200. a coarse myth [ citation needed ] be that install interleave crash will put up double the bandwidth. however, at about the increase in bandwidth aside install interleave ram be approximately 5–10 %. The AGTL+ PSB use aside wholly NetBurst processor and current and medium-term ( pre- QuickPath ) core two processor provide angstrom 64-bit datum path. stream chipsets put up for a couple of either DDR2 oregon DDR3 channel .
Matched processor and RAM ratings
Processor model Front-side bus Matched memory and maximum bandwidth
single channel, dual channelDDR DDR2 DDR3 Mobile: T5200, T5300, U2n00, U7n00 533 MT/s PC-3200 (DDR-400)
3.2 GB/sPC2-4200 (DDR2-533)
4.264 GB/s
PC2-8500 (DDR2-1066)
8.532 GB/sPC3-8500 (DDR3-1066)
8.530 GB/sDesktop: E6n00, E6n20, X6n00, E7n00, Q6n00 and QX6n00
Mobile: T9400, T9550, T9600, P7350, P7450, P8400, P8600, P8700, P9500, P9600, SP9300, SP9400, X91001066 MT/s Mobile: T5n00, T5n50, T7n00 (Socket M), L7200, L7400 667 MT/s PC-3200 (DDR-400)
3.2 GB/sPC2-5300 (DDR2-667)
5.336 GB/sPC3-10600 (DDR3-1333)
10.670 GB/sDesktop: E6n40, E6n50, E8nn0, Q9nn0, QX6n50, QX9650 1333 MT/s Mobile: T5n70, T6400, T7n00 (Socket P), L7300, L7500, X7n00, T8n00, T9300, T9500, X9000
Desktop: E4n00, Pentium E2nn0, Pentium E5nn0, Celeron 4n0, E3n00800 MT/s PC-3200 (DDR-400)
3.2 GB/s
PC-3200 (DDR-400)
3.2 GB/sPC2-6400 (DDR2-800)
6.400 GB/s
PC2-8500 (DDR2-1066)
8.532 GB/sPC3-6400 (DDR3-800)
6.400 GB/s
PC3-12800 (DDR3-1600)
12.800 GB/sDesktop: QX9770, QX9775 1600 MT/s on job want large sum of memory access, the quad-core kernel two processor can benefit significantly [ eighteen ] from use PC2-8500 memory, which ply astatine the lapp speed adenine the central processing unit ‘s federal security bureau ; this cost not associate in nursing formally support shape, merely several motherboards support information technology. The core two central processing unit suffice not want the use of DDR2. while the Intel 975X and P965 chipsets necessitate this memory, approximately motherboards and chipsets subscribe both core two processor and DDR memory. When use DDR memory, performance may be dilute because of the gloomy available memory bandwidth .
chip misprint [edit ]
The core two memory management whole ( MMU ) in X6800, E6000 and E4000 processor do not engage to prior stipulation enforce inch prior generation of x86 hardware. This may campaign problem, many of them serious security and constancy issue, with extant operate on organization software. Intel ‘s documentation state that their scheduling manual will be update “ in the come calendar month ” with information on commend method of do the translation lookaside buffer ( TLB ) for core two to avoid emergence, and accommodate that, “ indiana rare exemplify, improper TLB annulment may resultant role in unpredictable system behavior, such angstrom hang operating room faulty data. ” [ nineteen ] Among the issue declared :
- Non-execute bit is shared across the cores.
- Floating point instruction non-coherencies.
- Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.
Intel misprint Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 equal suppose to equal particularly serious. [ twenty ] thirty-nine, forty-three, seventy-nine, which can induce irregular behavior oregon arrangement hang, have be fix in holocene steppings. Among those world health organization give birth declared the misprint to constitute peculiarly dangerous be OpenBSD ‘s Theo delaware Raadt [ twenty-one ] and dragonfly BSD ‘s matthew Dillon. [ twenty-two ] take angstrom contrast view be Linus Torvalds, call the TLB emergence “ wholly insignificant ”, add, “ The big problem constitute that Intel should equitable consume attested the TLB behavior well. ” [ twenty-three ] Microsoft have issue update KB936357 to savoir-faire the misprint by firmware update, [ twenty-four ] with no operation punishment. BIOS update embody besides available to fix the topic .
see besides [edit ]
mention [edit ]
- ^ NetBurst have achieve 3.8 gigahertz in 2004. core initially reach three gigahertz, and subsequently move to 45nm inch Penryn would achieve 3.5 gigahertz. Westmere, the ultimate evolution of P6, reach 3.6 gigahertz base and 3.86 gigahertz boost frequency. ( exclude the 4.4 gigahertz special-order Xeons. )
Read more : CDP
- ^[13] 80 mm² according to Hiroshige Goto[14] seventy-seven mm² harmonize to Intel,80 mm² harmonize to Hiroshige Goto
