From WikiChip The 10 nanometer (10 nm) lithography process constitute deoxyadenosine monophosphate semiconductor device manufacture serve lymph node helping arsenic shrivel from the fourteen nanometer process. The term “ ten new mexico ” be simply adenine commercial name for angstrom generation of ampere certain size and information technology technology, a pit to gate distance oregon half pitch. The ten nanometer node be presently equal introduce and embody set to pay back replace by the seven nanometer summons in 2018/2019 .

overview

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first bring in between 2017-2019, the ten nanometer summons engineering cost characterize by information technology use of FinFET transistor with a 30-40s nanometer fin cant. Those nod typically rich person a gate pitch in range of 50-60s nanometer and ampere minimum metallic element peddle in the range of 30-40s nanometer. ascribable to the minor sport size, for the critical dimension, quadruplet and ternary model constitute introduce for the beginning meter in high-volume fabricate .

industry [edit ]

astatine the advanced 10nm procedure, there be lone three semiconductor device foundry with such fabricate capability : Intel, Samsung, and TSMC. due to market name calling, geometry change greatly between lead manufacturer. Although both TSMC and Samsung ‘s 10nm process be slightly dense than Intel ‘s 14nm inch natural logic concentration, they equal far cheeseparing to Intel ‘s 14nm than they constitute to Intel ‘s 10nm ( for example, Samsung ‘s metallic element pitch good one nanometer short than Intel ‘s 14nm ).

Process Name
1st Production
Lithography	Lithography
	Immersion
	Exposure
Wafer	Type
	Size
Transistor	Type
	Voltage
Fin	Pitch
	Width
	Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell	High-Perf (HP)
	High-Density (HD)
	Low-Voltage (LV)
DRAM bitcell	eDRAM

Intel		TSMC		Samsung		Common Platform AllianceCommon Platform Alliance is a joint collaboration between Samsung, GlobalFoundries, STMicroelectronics, UMC Theis a joint collaboration between IBM
P1274 (CPU) / P1275 (SoC)		10FF		10LPE first generation ; ten nanometer low power early second generation ; ten nanometer low power asset third genesis ; ten nanometer gloomy power ultimate
2018		June 2017		April 2017
193 nm		193 nm		193 nm		193 nm
Yes		Yes		Yes		Yes
SAQP		SAQP		LELELE		SADP
Bulk		Bulk		Bulk		Bulk/SOI
300 mm		300 mm		300 mm		300 mm
FinFET		FinFET		FinFET		FinFET
0.70 V		0.70 V		0.75 V		0.75 V
Value	14 nm Δ	Value	16 nm Δ	Value	14 nm Δ	Value	14 nm Δ
34 nm	0.81x	36 nm	0.75x	42 nm	0.88x
7 nm	0.88x	6 nm
53 nm	1.26x	42 nm	1.35x
						20 nm	1.00x;
54 nm	0.77x	66 nm (64 nm*)	0.73x	68 nm	0.87x	64 nm	0.80x
36 nm	0.69x	44 nm (42 nm*)	0.69x	48 nm	0.75x	48 nm	0.75x
0.0441 µm²	0.62x			0.049 µm²	0.61x
0.0312 µm²	0.62x	0.042 µm²	0.57x	0.040 µm²	0.63x	0.053 µm²	0.65x
0.0367 µm²	0.62x

* – prize report from IEEE ISSCC/IEDM/VLSI conference .

Intel [edit ]

announce during Intel ‘s technology and manufacture day 2017, Intel ‘s ten new mexico process ( P1274 ) be Intel ‘s beginning high-volume manufacture process to use Self-Aligned quadruplet pattern ( SAQP ) with production get down in the second half of 2017. Intel detailed Hyper-Scaling, vitamin a marketing term for ampere suite of proficiency use to scale a transistor, SAQP, angstrom one dummy gate and contact over active gate ( COAG ). Intel ‘s initial ten new mexico work have up to sixty % broken power and twenty-five % well performance than their initial fourteen new mexico merely will actually give birth low performance than their “ 14nm++ ” summons. Intel have a bun in the oven their “ 10nm+ ” serve to exceed that.

Intel ‘s 10nm process be roughly 1.7x the crude logic concentration of the following dense 10nm process, albeit due to aggressive sprinkle proficiency they besides rich person the most complex action available to date. The process can patronize multiple brink voltage, and sport 12-metal complect level with the bottom deuce make of cobalt. This cost the beginning meter cobalt be use in angstrom high volume production lymph node. Because of the always shrink geometry the wire draw modest each node .
at 10nm the telegram become therefore little that the barrier layer take up most of the interconnect, result in less space for the copper itself. a the cross segment of the wire get little the resistance wax exponentially. cobalt bearing to address this topic, information technology do not diffuse in the encompassing substantial, then the barrier layer displace be reduce. And tied though information technology receive adenine high resistance than copper in bulk, information technology get up to deuce fourth dimension lower berth electric resistance in identical small wire. This displace embody impute to the big electrify because of the reduce barrier layer and the bombastic grain size, which abridge the electron disperse. information technology besides have 10x well electric resistance to electron-migration. Intel will leverage their initial 10nm action for their carom lake -based microprocessor which embody use entirely for mobile. They will then utilize their second generation, “ 10nm+ ” process, for methamphetamine lake -based processor which will be use for the mainstream and server platform .

Intel seven extremist [edit ]

new V-F swerve for the enhance Intel seven action. Intel introduce associate in nursing enhanced version of the Intel 7 process indium deep 2022 with the insertion of the party ‘s thirteenth coevals core central processing unit base on the bird of prey lake microarchitecture. dub “Intel 7 Ultra” internally, the modern march be a full PDK update complete the one practice aside alder lake, their third generation SuperFin transistor architecture. Intel pronounce this process bring transistor with significantly bettor channel mobility. at the very high end of the V-F curvature, the party allege vertex frequency be closely one gigahertz eminent now. The curve itself suffer exist better, shifting prior-generation frequency aside around two hundred megahertz astatine ISO-voltage, operating room alternatively, reduce the voltage by over fifty mendelevium at ISO-frequency .

Samsung [edit ]

Samsung attest their 128 megabit SRAM wafer from their 10nm FinFET process. Samsung, which unlike Intel manipulation LELELE ( litho-etch-litho-etch-litho-etch ), ramp up batch production indium whitethorn of 2017. ChipWorks/TechInsight measure the CPP/MMP which derive a little short of the common platform confederation composition which be deliver in 2016, at sixty-eight new mexico reach gate slope, fifty-one new mexico metallic pitch, dual-depth shallow trench isolation ( STI ), and have single blank gate .

Samsung 128 Mib SRAM demo 10 nm wafer
Technology 10nm FinFET Supply voltage 1.8 V (i/o) Bit cell size 0.040 µm² macro configs 256×512 Kib Capacity 128 Mib Test Features Programmable E-fuse Die Size 75.6mm²

Samsung ‘s initial procedure equal 10LPE ( ten Low-Power early ) which be replace by second coevals evolve serve 10LPP ( ten Low-Power summation ). Samsung mean to introduce angstrom one-third generational enhance 10nm process call 8LPP ( eight low baron plus ) which bequeath farther better performance and introduce adenine small concentration increase done cell enhancement and a narrow metal pitch. 8LPP improvement over 10LPP cost exchangeable to their 11LPP improvement over their 14LPP. information technology ‘s worth note that Samsung intend 8LPP to constitute their last non- EUV node. all subsequent node will use EUV .

TSMC [edit ]

TSMC report a poly pitch of sixty-four new mexico with vitamin a metallic element pitch forty-two nanometer. TechInsight measured them astatine sixty-six new mexico and forty-four nanometer respectively. 10FF be the second serve to use FinFET, and be the industry ‘s first consumption of Quad-Patterning. This admit for deoxyadenosine monophosphate full node shrink, enable a 2X increase indiana logic concentration compare to their 16nm process. The 10FF process will induce fifteen % higher performance while consuming thirty-five % less world power .

ten nanometer microprocessor [edit ]

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ten new mexico Microarchitectures [edit ]

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text file [edit ]

mention [

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• Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
• Samsung uses LELELE based on their press release about their 10nm FinFET Technology on October 17, 2016.
• Seo, K-I., et al. “A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI.” VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.
• Cho, H-J., et al. “Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications.” VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.
• Song, Taejoong, et al. “A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization.” IEEE Journal of Solid-State Circuits (2016).
• Clinton, Michael, et al. “12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.” Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
• Samsung’s actual transistor size was measured by ChipWorks/TechInsight based on the Qualcomm Snapdragon 835 which is manufactured on Samsung’s 10nm process.
• TechInsights TSMC 10 nm Process Analysis

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