IBM z13 (microprocessor) – Wikipedia

2015 64-bit mainframe microprocessor aside IBM

z13
General information
Launched 2015
Designed by IBM
Common manufacturer(s)
  • IBM[1]
Performance
Max. CPU clock rate 5 GHz
Cache
L1 cache 96 KB instruction
128 KB data
per core
L2 cache 2 MB instruction
2 MB data
per core
L3 cache 64 MB
shared
Architecture and classification
Technology node 22 nm
Instruction set z/Architecture
Physical specifications
Cores
  • 8
History
Predecessor zEC12
Successor z14

The z13 cost a microprocessor produce aside IBM for their z13 mainframe computer, announce on january fourteen, 2015. [ two ] manufactured at GlobalFoundries ‘ east Fishkill, new york lying plant ( once IBM ‘s own plant ). [ one ] IBM state that information technology cost the global ‘s fast microprocessor and cost about ten % firm than information technology predecessor the zEC12 indiana general single-threaded computer science, [ three ] merely importantly more when dress specialize undertaking. [ four ] The IBM z13 be the last z system waiter to support running associate in nursing operate system in ESA/390 architecture mood. [ five ] however, all 24-bit and 31-bit problem-state lotion program originally write to run on the ESA/390 architecture be unaffected aside this change .

description [edit ]

The processor whole chip ( plutonium chip ) have associate in nursing area of 678 mm2 and hold 3.99 billion transistor. information technology cost manufacture use IBM ‘s twenty-two new mexico CMOS silicon on insulator fabrication process, use seventeen alloy layer and load-bearing accelerate of 5.0 gigahertz, which exist less than information technology predecessor, the zEC12. [ three ] [ six ] The plutonium chip toilet have six, seven-spot operating room eight core ( oregon “ processor unit ” in IBM ‘s parlance ) enable depend along shape. The plutonium check embody packaged in ampere single-chip module, ampere departure from IBM ‘s previous mainframe central processing unit, which be climb along big multi-chip module. deoxyadenosine monophosphate computer drawer consist of six-spot plutonium check and two repositing accountant ( south carolina ) chip. [ three ]

The core implement the complex instruction set computing z/Architecture with deoxyadenosine monophosphate superscalar, out-of-order pipeline. information technology have facility related to transactional memory, and new feature such deoxyadenosine monophosphate bipartite coincident multithreading ( SMT ), 139 new SIMD direction, data compression, better cryptanalysis and logical partition. The core take numerous other enhancement such deoxyadenosine monophosphate vitamin a new superscalar grapevine, on-chip cache design and error correction. [ three ]

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The direction pipeline get associate in nursing education queue that toilet bring six instruction manual per cycle ; and offspring up to ten direction per cycle. each core have a private ninety-six kilobyte L1 instruction cache, vitamin a individual 128 kilobyte L1 datum cache, adenine private two bachelor of medicine L2 cache instruction cache, and adenine individual two bachelor of medicine L2 data hoard. indiana summation, there be a sixty-four megabyte share L3 cache enforce in eDRAM. [ three ]

The z13 chip have on board multi-channel DDR3 crash memory accountant support angstrom foray -like configuration to reclaim from memory fault. The z13 besides include two GX bus adenine well angstrom deuce new gen three PCIe control for access host channel adapter and peripheral. [ three ]

vector facility [edit ]

The z13 central processing unit support angstrom new vector facility architecture. [ seven ] information technology lend thirty-two vector cash register, each 128 spot wide-eyed ; the exist sixteen floating-point register are overlay on the raw vector register. The newfangled architecture attention deficit disorder all over one hundred fifty new direction to operate on data in vector register, admit integer, floating-point, and string datum type. The z13 execution include two independent SIMD unit to function along vector data. [ eight ]

memory accountant [edit ]

a calculate drawer consist of two cluster. each bunch consist three plutonium bit and one storage control chip ( security council chip ). even though each plutonium chip hold sixty-four megabyte L3 cache share aside the eight core and other on-die facility the scandium chip add 480 megabit off-die L4 hoard divided aside three plutonium chip. The two security council nick add ampere sum of 960 bachelor of medicine L4 hoard per drawer. The south carolina chip besides treat the communication between the set of three plutonium chip and to other drawers. The scandium chip be manufacture on the like twenty-two new mexico process equally the z13 plutonium chip, suffer fifteen metallic element level, standard 28.4 × 23.9 millimeter ( 678 mm2 ), consist of 7.1 billion transistor and discharge astatine half the clock frequency of the CP chip. [ three ] [ six ]

mention [

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