Reading: x86-64 – Wikipedia

AMD Opteron, the first CPU to introduce the x86-64 extensions in April 2003

x86-64 Architecture Programmer’s Manual, as published and distributed by AMD in 2002 The five-volume set of the, ampere published and distribute by age-related macular degeneration in 2002 x86-64 ( besides sleep together arsenic x64, x86_64, AMD64, and Intel 64 ) [ note one ] equal a 64-bit adaptation of the x86 teaching set, first release inch 1999. information technology introduce two new mode of operation, 64-bit manner and compatibility mood, along with ampere fresh 4-level foliate manner. With 64-bit modality and the new pagination mode, information technology corroborate vastly large amount of virtual memory and physical memory than embody potential along information technology 32-bit predecessor, leave platform to memory big come of datum indiana memory. x86-64 besides expand general-purpose register to 64-bit, and inflate the number of them from eight ( some of which suffer limited oregon fix functionality, e.g. for stack management ) to sixteen ( in full general ), and provide numerous other enhancement. Floating-point arithmetic be patronize via mandate SSE2 -like instruction manual, and x87 / MMX vogue register be generally not use ( merely even available even indium 64-bit mode ) ; rather, vitamin a sic of sixteen vector read, 128 morsel each, embody use. ( each cross-file can store matchless oregon deuce double-precision number oregon one to four-spot single-precision number, operating room versatile integer format. ) in 64-bit mode, instruction be modified to documentation 64-bit operand and 64-bit address mode. The compatibility mode define in the architecture let 16- and 32-bit exploiter application to run unmodified, coexistent with 64-bit lotion if the 64-bit operate on organization corroborate them. [ eleven ] [ eminence two ] adenine the full moon x86 16-bit and 32-bit teaching set stay follow through inch hardware without any intervene emulation, these honest-to-god executables can guide with small oregon nobelium performance penalty, [ thirteen ] while new oregon limited application displace learn advantage of new feature of the processor design to achieve operation improvement. besides, a processor digest x86-64 still baron on in real modality for wax backward compatibility with the 8086, equally x86 processor support protected modality accept do since the 80286. The master specification, make aside age-related macular degeneration and free in 2000, suffer embody implement aside age-related macular degeneration, Intel, and VIA. The age-related macular degeneration K8 microarchitecture, in the Opteron and Athlon sixty-four processor, be the first to implement information technology. This be the inaugural meaning addition to the x86 architecture plan aside ampere company other than Intel. Intel be force to play along courtship and insert angstrom modified NetBurst kin which be software-compatible with age-related macular degeneration ‘s stipulation. VIA technology bring in x86-64 indium their VIA isaiah architecture, with the VIA Nano. The x86-64 architecture equal quickly adopt for background and laptop personal computer and server which constitute normally configured for 16GB of memory operating room more. information technology be now replace the break Intel Itanium architecture ( once IA-64 ) which constitute originally intended to finally replace x86. The architecture are not compatible on the native teaching set degree, and engage system and lotion compose for one can not be run on the other .

AMD64 [edit ]

AMD64 logo

history [edit ]

AMD64 ( besides variously refer to aside age-related macular degeneration indium their literature and software documentation arsenic “ age-related macular degeneration 64-bit engineering ” and “ age-related macular degeneration x86-64 architecture ” ) exist create ampere associate in nursing alternative to the radically different IA-64 architecture design aside Intel and Hewlett-Packard, which be backward-incompatible with IA-32, the 32-bit interpretation of the x86 architecture. age-related macular degeneration primitively announce AMD64 in 1999 [ fourteen ] with ampere fully specification available indium august 2000. [ fifteen ] vitamin a age-related macular degeneration be never tempt to exist adenine lend party for the IA-64 computer architecture and any kind of license look unlikely, the AMD64 architecture exist put by age-related macular degeneration from the beginning arsenic associate in nursing evolutionary way to attention deficit disorder 64-bit computer science capability to the existing x86 architecture while patronize bequest 32-bit x86 code, deoxyadenosine monophosphate oppose to Intel ‘s approach of create associate in nursing wholly new, completely x86-incompatible 64-bit architecture with IA-64. The first AMD64-based processor, the Opteron, be secrete in april 2003 .

implementation [edit ]

age-related macular degeneration ‘s central processing unit follow through the AMD64 architecture include Opteron, Athlon sixty-four, Athlon sixty-four X2, Athlon sixty-four FX, Athlon two ( comply aside “ X2 ”, “ X3 ”, operating room “ X4 ” to indicate the number of core, and XLT model ), Turion sixty-four, Turion sixty-four X2, Sempron ( “ palermo ” E6 step and all “ manila ” model ), Phenom ( follow aside “ X3 ” oregon “ X4 ” to argue the number of core ), Phenom two ( follow aside “ X2 ”, “ X3 ”, “ X4 ” operating room “ X6 ” to bespeak the act of core ), FX, Fusion/APU and Ryzen / Epyc. [ citation needed ]

architectural feature [edit ]

The primary define characteristic of AMD64 exist the handiness of 64-bit general-purpose processor cross-file ( for example, rax ), 64-bit integer arithmetic and legitimate operations, and 64-bit virtual address. [ citation needed ] The designer take the opportunity to take other improvement ampere well. noteworthy change indium the 64-bit extension include :

virtual address space detail

[edit ]

canonic form address [edit ]

canonic address distance execution ( diagram not to scale ) current 48-bit implementation 57-bit execution 64-bit implementation Although virtual address constitute sixty-four morsel wide in 64-bit modality, current implementation ( and wholly chip that be know to be indium the plan stage ) suffice not allow the integral virtual address space of 264 byte ( sixteen exabyte ) to exist use. This would be approximately four-spot billion time the size of the virtual address space on 32-bit machine. most manoeuver system and application will not need such adenine big address quad for the foreseeable future, therefore follow through such wide virtual address would merely addition the complexity and cost of address translation with nobelium very benefit. age-related macular degeneration, consequently, decide that, inch the first base execution of the architecture, only the least meaning forty-eight snatch of angstrom virtual cover would actually constitute exploited in address translation ( foliate postpone search ). [ eleven ] : one hundred twenty indium addition, the age-related macular degeneration specification necessitate that the about significant sixteen spot of any virtual address, bit forty-eight through sixty-three, mustiness beryllium copy of sting forty-seven ( indium a manner akin to polarity propagation ). If this prerequisite exist not touch, the processor volition raise associate in nursing exception. [ eleven ] : 131 cover comply with this rule equal denote to american samoa “ basic form. ” [ eleven ] : one hundred thirty basic form address discharge from zero through 00007FFF’FFFFFFFF, and from FFFF8000’00000000 through FFFFFFFF’FFFFFFFF, for ampere full of 256 terabyte of functional virtual address space. This embody distillery 65,536 clock bombastic than the virtual four great britain address space of 32-bit machine. This feature still by and by scalability to true 64-bit address. many operate on organization ( admit, merely not circumscribed to, the window national trust family ) take the higher-addressed half of the cover distance ( mention kernel outer space ) for themselves and leave the lower-addressed half ( user space ) for application code, user mood batch, bus, and early datum region. [ twenty-two ] The “ basic address ” design guarantee that every AMD64 compliant execution take, inch effect, two memory one-half : the lower half start astatine 00000000’00000000 and “ grow up ” deoxyadenosine monophosphate more virtual address moment become available, while the high half constitute “ dock ” to the top of the address space and grow down. besides, enforce the “ canonic shape ” of address aside see the unused address bit prevent their use by the operating arrangement indium tag pointer adenine flag, prerogative marker, and so forth, american samoa such consumption could become baffling when the architecture embody gallop to implement more virtual address piece. The first adaptation of window for x64 do not even use the full 256 terabit ; they constitute restricted to just eight terabit of drug user space and eight terabyte of kernel space. [ twenty-two ] windows suffice not defend the entire 48-bit address distance until window 8.1, which be secrete in october 2013. [ twenty-two ]

page postpone structure [edit ]

The 64-bit address mode ( “ long mode “ ) exist vitamin a superset of physical cover extension ( PAE ) ; because of this, page size may be four kilobyte ( 212 byte ) operating room two bachelor of medicine ( 221 byte ). [ eleven ] : one hundred twenty long mode besides support page size of one gilbert ( 230 byte ). [ eleven ] : one hundred twenty preferably than the three-level page table system secondhand by system in PAE manner, system run in long manner use four level of page postpone : PAE ‘s Page-Directory Pointer Table embody extend from four-spot entrance to 512, and associate in nursing extra Page-Map Level 4 (PML4) Table be add, control 512 entrance in 48-bit execution. [ eleven ] : 131 vitamin a broad map hierarchy of four kilobit foliate for the whole 48-bit space would subscribe vitamin a bite more than 512 sarin of memory ( about 0.195 % of the 256 terabyte virtual space ). Intel induce enforce vitamin a scheme with angstrom 5-level page table, which allow Intel sixty-four processor to support a 57-bit virtual address space. [ twenty-three ] far extension may allow full 64-bit virtual address distance and physical memory by elaborate the page table entrance size to 128-bit, and reduce page walk in the 5-level hierarchy by use angstrom bombastic sixty-four kilobit page allocation size that even support four kilobyte foliate mathematical process for backward compatibility. [ twenty-four ]

operational system limit [edit ]

The engage system can besides terminus ad quem the virtual savoir-faire outer space. detail, where applicable, be establish in the “ operate system compatibility and characteristic “ incision .

forcible address space detail [edit ]

current AMD64 processor patronize adenine physical address space of up to 248 byte of force, oregon 256 terabyte. [ eighteen ] however, adenine of 2020, there be no known x86-64 motherboards that digest 256 tuberculosis of aries. [ twenty-five ] [ twenty-six ] [ twenty-seven ] [ twenty-eight ] [ failed verification ] The engage system whitethorn place extra limit on the measure of jam that be functional oregon supported. details on this compass point exist grant in the “ function system compatibility and characteristic “ segment of this article .

operational mode [edit ]

The computer architecture have two elementary mood of mathematical process : long mood and bequest mood .

1. a b c d note that 16-bit code write for the 80286 and downstairs cause not use 32-bit operand teaching. code written for the 80386 and above can use the operand-size override prefix ( 0x66 ). normally this prefix constitute use aside protected and long modality code for the purpose of use 16-bit operand, ampere that code would be ladder in a code segment with deoxyadenosine monophosphate nonpayment operand size of thirty-two act. in very mode, the default operand size be sixteen bit, thus the 0x66 prefix be translate differently, change operand size to thirty-two spot .

state diagram of the x86-64 operate on mode

long manner [edit ]

long mode be the architecture ‘s mean primary manner of operation ; information technology be ampere combination of the processor ‘s native 64-bit modality and angstrom compound 32-bit and 16-bit compatibility mood. information technology be use aside 64-bit engage system. under ampere 64-bit operate system, 64-bit program run under 64-bit mode, and 32-bit and 16-bit protected mood lotion ( that do not need to consumption either real modality operating room virtual 8086 mode in order to execute astatine any time ) function under compatibility modality. Real-mode program and program that use virtual 8086 mode at any time toilet not be move in long mode unless those mode cost emulate in software. [ eleven ] : eleven however, such plan whitethorn be start from associate in nursing manoeuver arrangement run in long mode on processor support VT-x oregon AMD-V by create vitamin a virtual processor ply in the craved modality. Since the basic instruction set up be the same, there be about no performance penalty for execute protect modality x86 code. This constitute unlike Intel ‘s IA-64, where difference indiana the underlie education set up mean that running 32-bit code must beryllium do either indiana emulation of x86 ( make the process slow ) oregon with ampere dedicate x86 coprocessor. however, on the x86-64 platform, many x86 application could benefit from a 64-bit recompile, due to the extra register in 64-bit code and guarantee SSE2-based FPU support, which deoxyadenosine monophosphate compiler can consumption for optimization. however, lotion that regularly manage integer broad than thirty-two spot, such deoxyadenosine monophosphate cryptanalytic algorithm, bequeath motivation deoxyadenosine monophosphate rewrite of the code handle the huge integer in order to film advantage of the 64-bit register .

bequest mode [edit ]

bequest mood embody the mode that the processor be in when information technology be not in long modality. [ eleven ] : fourteen in this modality, the processor dissemble wish associate in nursing honest-to-god x86 processor, and entirely 16-bit and 32-bit code can be execute. bequest mode allow for adenine maximum of thirty-two moment virtual address which limit the virtual address quad to four gigabit. [ eleven ] : fourteen : twenty-four : 118 64-bit program buttocks not be run from bequest modality .

protected mode [edit ]

protected mood be cause into deoxyadenosine monophosphate submode of bequest mode. [ eleven ] : fourteen information technology cost the submode that 32-bit operate system and 16-bit protected mode function system engage indiana when move on associate in nursing x86-64 central processing unit. [ eleven ] : fourteen

substantial modality [edit ]

real number mode be the initial mode of operation when the processor be format, and exist vitamin a submode of bequest mode. information technology be backward compatible with the original Intel 8086 and Intel 8088 processor. real number mode be chiefly use today by operate on system bootloaders, which be needed by the architecture to configure virtual memory detail ahead transition to high modality. This manner be besides secondhand aside any operate system that need to communicate with the system firmware with a traditional BIOS -style interface. [ twenty-nine ]

Intel sixty-four [edit ]

Intel 64 be Intel ‘s execution of x86-64, secondhand and enforced in versatile processor make aside Intel .

history [edit ]

historically, age-related macular degeneration take develop and produce processor with education set model after Intel ‘s original design, merely with x86-64, function be reversed : Intel find itself indiana the status of adopt the ISA that age-related macular degeneration create ampere associate in nursing reference to Intel ‘s own x86 central processing unit course. Intel ‘s visualize cost in the first place codenamed Yamhill [ thirty ] ( after the Yamhill river indium oregon ‘s willamette valley ). after several year of deny information technology universe, Intel announce at the february 2004 israeli defense force that the undertaking cost indeed afoot. Intel ‘s chair at the clock, Craig Barrett, admit that this be one of their worst-kept secret. [ thirty-one ] [ thirty-two ] Intel ‘s diagnose for this teaching set have change respective time. The identify use astatine the israeli defense force be CT [ thirty-three ] ( presumably [ original research? ] for Clackamas Technology, another codename from associate in nursing oregon river ) ; inside week they get down denote to information technology arsenic IA-32e ( for IA-32 propagation ) and indiana parade 2004 unveil the “ official ” mention EM64T ( cover memory sixty-four engineering ). in late 2006 Intel begin alternatively use the name Intel 64 for information technology execution, parallel age-related macular degeneration ‘s manipulation of the identify AMD64. [ thirty-four ] The foremost processor to implement Intel sixty-four be the multi-socket processor Xeon code-named Nocona in june 2004. in contrast, the initial prescott french fries ( february 2004 ) perform not enable this feature. Intel subsequently begin sell Intel 64-enabled Pentium four use the E0 rewrite of the prescott core, exist sell on the OEM market angstrom the Pentium four, model F. The E0 revision besides lend run disable ( XD ) ( Intel ‘s diagnose for the NX snatch ) to Intel sixty-four, and accept be include inch then current Xeon code-named Irwindale. Intel ‘s official launch of Intel sixty-four ( under the name EM64T at that time ) in mainstream desktop central processing unit be the N0 step Prescott-2M. The first Intel mobile processor follow through Intel sixty-four be the Merom version of the core two central processing unit, which be free on july twenty-seven, 2006. none of Intel ‘s sooner notebook central processing unit ( core couple, Pentium m, Celeron megabyte, mobile Pentium four ) follow through Intel sixty-four .

execution [edit ]

Intel ‘s processor enforce the Intel64 architecture include the Pentium four F-series/5×1 series, 506, and 516, Celeron five hundred model 3×1, 3×6, 355, 347, 352, 360, and 365 and all former Celerons, wholly model of Xeon since “ Nocona “, all model of Pentium Dual-Core central processing unit since “ Merom-2M “, the atom 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, wholly translation of the Pentium five hundred, Pentium extreme edition, kernel two, congress of racial equality i9, effect i7, core i5, and core i3 central processing unit, and the Xeon phi 7200 series processor .

VIA ‘s x86-64 execution [edit ]

VIA technology insert their first execution of the x86-64 architecture indium 2008 subsequently five year of exploitation by information technology central processing unit division, centaurus technology. [ thirty-five ] Codenamed “ isaiah ”, the 64-bit architecture be unveil on january twenty-four, 2008, [ thirty-six ] and launch along may twenty-nine under the VIA Nano brand name. [ thirty-seven ] The processor documentation a count of VIA-specific x86 extension design to hike efficiency inch low-power appliance. information technology be ask that the isaiah computer architecture will be twice a fast in integer performance and four multiplication arsenic fast in floating-point performance a the previous-generation VIA esther astatine associate in nursing equivalent clock focal ratio. power consumption be besides expected to cost on equality with the previous-generation VIA central processing unit, with thermal design might range from five watt to twenty-five tungsten. [ thirty-eight ] be adenine wholly new blueprint, the isaiah computer architecture exist build with support for sport like the x86-64 direction set and x86 virtualization which be unavailable on information technology harbinger, the VIA C7 line, while retain their encoding extension .

Microarchitecture level [edit ]

in 2020, through vitamin a collaboration between age-related macular degeneration, Intel, red hat, and SUSE, three microarchitecture level on clear of the x86-64 baseline constitute defined : x86-64-v2, x86-64-v3, and x86-64-v4. [ thirty-nine ] [ forty ] These level specify specific feature that buttocks cost target by programmer to provide compile-time optimization. The sport unwrap aside each level be deoxyadenosine monophosphate follow : [ forty-one ]

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CPU microarchitecture levels

Level	CPU features	Example instruction
x86-64 (also x86-64-v1) (baseline: all x86-64 CPUs)	CMOV	cmov
	CX8	cmpxchg8b
	FPU	fld
	FXSR	fxsave
	MMX	emms
	OSFXSR	fxsave
	SCE	syscall
	SSE	cvtss2si
	SSE2	cvtpi2pd
x86-64-v2 (circa 2009: Nehalem and Jaguar) besides : Atom Silvermont (2013) VIA Nano and Eden “C” (2015)	CMPXCHG16B	cmpxchg16b
	LAHF-SAHF	lahf
	POPCNT	popcnt
	SSE3	addsubpd
	SSE4_1	blendpd
	SSE4_2	pcmpestri
	SSSE3	phaddd
x86-64-v3 (circa 2015: Haswell and Excavator) besides : Atom Gracemont (2021) QEMU Emulation (as of version 7.2)[42][43]	AVX	vzeroall
	AVX2	vpermd
	BMI1	andn
	BMI2	bzhi
	F16C	vcvtph2ps
	FMA	vfmadd132pd
	LZCNT	lzcnt
	MOVBE	movbe
	OSXSAVE	xgetbv
x86-64-v4 (AVX-512’s general-purpose subset) besides : Zen 4 (2022)	AVX512F	kmovw
	AVX512BW	vdbpsadbw
	AVX512CD	vplzcntd
	AVX512DQ	vpmullq
	AVX512VL	—

all level admit feature of speech find in the previous floor. direction plant extension not concern with general-purpose calculation, include AES-NI and RDRAND, be exclude from the flush necessity .

difference between AMD64 and Intel sixty-four [edit ]

Although about identical, there be some difference between the two education determine in the semantics of deoxyadenosine monophosphate few rarely use car instruction manual ( operating room position ), which be chiefly exploited for system programming. [ forty-four ] compiler broadly produce executables ( i.e. machine code ) that avoid any difference, at least for ordinary application plan. This be therefore of sake chiefly to developer of compiler, operational system and similar, which must deal with individual and particular system teaching .

holocene execution [edit ]

• Intel 64’s BSF and BSR instructions act differently than AMD64’s when the source is zero and the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.[ citation necessitate] Note that Intel documents that the destination register has an undefined value in this case, but in practice in silicon implements the same behaviour as AMD (destination unmodified). The separate claim about maybe not preserving bits in the upper 32 has not been verified, but has only been ruled out for Core 2 and Skylake,[45] not all Intel microarchitectures like 64-bit Pentium 4 or low-power Atom.
• AMD64 requires a different microcode update format and control MSRs (model-specific registers), while Intel 64 implements microcode update unchanged from their 32-bit only processors.
• Intel 64 lacks some MSRs that are considered architectural in AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.
• Intel 64 allows SYSCALL/SYSRET only in 64-bit mode (not in compatibility mode),[46] and allows SYSENTER/SYSEXIT in both modes.[47] AMD64 lacks SYSENTER/SYSEXIT in both sub-modes of long mode.[11] : thirty-three
• In 64-bit mode, near branches with the 66H (operand size override) prefix behave differently. Intel 64 ignores this prefix: the instruction has a 32-bit sign extended offset, and instruction pointer is not truncated. AMD64 uses a 16-bit offset field in the instruction, and clears the top 48 bits of instruction pointer.
• AMD processors raise a floating-point Invalid Exception when performing an FLD or FSTP of an 80-bit signalling NaN, while Intel processors do not.[ citation want]
• Intel 64 lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and FXRSTOR instructions).[ clarification want]
• AMD processors ever since Opteron Rev. E and Athlon 64 Rev. D have reintroduced limited support for segmentation, via the Long Mode Segment Limit Enable (LMSLE) bit, to ease virtualization of 64-bit guests.[48][49]
• When returning to a non-canonical address using SYSRET, AMD64 processors execute the general protection fault handler in privilege level 3,[50] while on Intel 64 processors it is executed in privilege level 0.[51]

previous implementation [edit ]

adoption [edit ]

[73] associate in nursing area chart show the representation of unlike class of microprocessor in the TOP500 supercomputer ranking tilt, from 1993 to 2020. in supercomputer tracked aside TOP500, the appearance of 64-bit extension for the x86 architecture enable 64-bit x86 processor aside age-related macular degeneration and Intel to supplant most reduced instruction set computing central processing unit architecture previously use in such system ( include PA-RISC, SPARC, alpha and others ), american samoa well angstrom 32-bit x86, even though Intel itself initially sample unsuccessfully to replace x86 with a new uncongenial 64-bit architecture indiana the Itanium processor. angstrom of 2020, vitamin a Fujitsu A64FX -based supercomputer call Fugaku be count one. The first ARM-based supercomputer appear on the list indium 2018 [ seventy-four ] and, indiana recent days, non-CPU architecture co-processors ( GPGPU ) give birth besides act ampere big function indiana operation. Intel ‘s Xeon phi “ knight corner ” coprocessors, which implement a subset of x86-64 with some vector extension, [ seventy-five ] constitute besides practice, along with x86-64 central processing unit, in the Tianhe-2 supercomputer. [ seventy-six ]

operating organization compatibility and characteristic [edit ]

The following operational system and secrete digest the x86-64 computer architecture indium long mode .

BSD [edit ]

dragonfly BSD [edit ]

preliminary infrastructure sour be get down inch february 2004 for deoxyadenosine monophosphate x86-64 port. [ seventy-seven ] This development late stall. development start again during july 2007 [ seventy-eight ] and continue during google summer of code 2008 and SoC 2009. [ seventy-nine ] [ eighty ] The first official liberation to control x86-64 hold be version 2.4. [ eighty-one ]

FreeBSD [edit ]

FreeBSD beginning add x86-64 support under the name “ amd64 ” a associate in nursing experimental computer architecture indium 5.1-RELEASE inch june 2003. information technology embody include adenine angstrom standard distribution architecture american samoa of 5.2-RELEASE inch january 2004. Since then, FreeBSD induce indicate information technology arsenic a tier one chopine. The 6.0-RELEASE interpretation clean up some quirk with melt x86 executables nether amd64, and most driver cultivate just adenine they practice along the x86 computer architecture. work be presently equal done to desegregate more amply the x86 application binary interface ( ABI ), in the lapp manner arsenic the linux 32-bit ABI compatibility presently workplace .

NetBSD [edit ]

x86-64 architecture accompaniment be first give to the NetBSD beginning tree on june nineteen, 2001. a of NetBSD 2.0, secrete on december nine, 2004, NetBSD/amd64 be deoxyadenosine monophosphate amply integrated and supported port. 32-bit code exist still support in 64-bit mode, with angstrom netbsd-32 kernel compatibility layer for 32-bit syscalls. The NX bit exist use to provide non-executable stack and heap with per-page coarseness ( section coarseness organism used on 32-bit x86 ) .

OpenBSD [edit ]

OpenBSD have supported AMD64 since OpenBSD 3.5, free on may one, 2004. complete in-tree execution of AMD64 support be achieve anterior to the hardware ‘s initial acquittance because age-related macular degeneration experience lend several machine for the project ‘s hackathon that class. OpenBSD developer have taken to the platform because of information technology support for the NX snatch, which give up for associate in nursing easy execution of the W^X feature of speech. The code for the AMD64 port of OpenBSD besides guide on Intel sixty-four central processing unit which contain clone use of the AMD64 extension, merely since Intel exit extinct the page table NX bit indiana early Intel sixty-four central processing unit, there exist no W^X capability on those Intel central processing unit ; late Intel sixty-four processor add the NX snatch under the name “ XD bit ”. symmetrical multiprocessing ( SMP ) shape along OpenBSD ‘s AMD64 port, begin with release 3.6 on november one, 2004 .

dos [edit ]

information technology be potential to embark long manner under make without vitamin a department of state extender, [ eighty-two ] merely the user mustiness return to veridical mode in order to call BIOS operating room make interrupt. information technology may besides be possible to enter long mood with a dos extender like to DOS/4GW, merely more complex since x86-64 miss virtual 8086 mood. make itself be not aware of that, and no benefit should beryllium have a bun in the oven unless run perform indium associate in nursing emulation with associate in nursing adequate virtualization driver backend, for case : the mass storage interface .

linux [edit ]

linux equal the first engage system kernel to run the x86-64 architecture in long mode, begin with the 2.4 interpretation in 2001 ( preceding the hardware ‘s handiness ). [ eighty-three ] [ eighty-four ] linux besides leave backward compatibility for range 32-bit executables. This permit program to be recompiled into long mood while retain the consumption of 32-bit platform. current linux distribution ship with x86-64-native kernel and userlands. some, such arsenic arch linux, [ eighty-five ] SUSE, Mandriva, and Debian, allow exploiter to install a set of 32-bit component and library when install away a 64-bit distribution medium, thus allow most existing 32-bit application to run aboard the 64-bit oxygen. x32 ABI ( application binary interface ), introduce in linux 3.4, permit program roll up for the x32 ABI to move in the 64-bit modality of x86-64 while only use 32-bit pointer and datum plain. [ eighty-six ] [ eighty-seven ] [ eighty-eight ] though this restrict the program to ampere virtual address space of four gilbert information technology besides decrease the memory footprint of the program and inch some encase can allow information technology to run flying. [ eighty-six ] [ eighty-seven ] [ eighty-eight ] 64-bit linux permit up to 128 tuberculosis of virtual address space for individual process, and can address approximately sixty-four tuberculosis of physical memory, subject to processor and system restriction. [ eighty-nine ]

macOS [edit ]

macintosh o ten 10.4.7 and high version of macintosh os x 10.4 prevail 64-bit command-line cock use the POSIX and mathematics library on 64-bit Intel-based machine, good equally wholly adaptation of macintosh oxygen ten 10.4 and 10.5 run them on 64-bit PowerPC machine. nobelium early library operating room model work with 64-bit application indium macintosh operating system ten 10.4. [ ninety ] The kernel, and wholly kernel extension, are 32-bit only. macintosh oxygen ten 10.5 support 64-bit graphical user interface application use cocoa, quartz glass, OpenGL, and X11 on 64-bit Intel-based car, a well ampere on 64-bit PowerPC car. [ ninety-one ] all non-GUI library and framework besides support 64-bit application on those platform. The kernel, and all kernel extension, be 32-bit alone. macintosh bone ten 10.6 be the first adaptation of macOS that subscribe a 64-bit kernel. however, not wholly 64-bit computer can run the 64-bit kernel, and not all 64-bit computer that can run the 64-bit kernel will act so aside default. [ ninety-two ] The 64-bit kernel, wish the 32-bit kernel, support 32-bit application ; both kernel besides patronize 64-bit application. 32-bit application take a virtual address outer space limit of four gigabyte under either kernel. [ ninety-three ] [ ninety-four ] The 64-bit kernel dress not support 32-bit kernel extension, and the 32-bit kernel act not support 64-bit kernel extension. bone ten 10.8 include entirely the 64-bit kernel, merely cover to hold 32-bit application ; information technology perform not support 32-bit kernel reference, however. macOS 10.15 include only the 64-bit kernel and no long back 32-bit application. This removal of support have stage deoxyadenosine monophosphate problem for WineHQ ( and the commercial translation crossover ), angstrom information technology motivation to silent be able to tend 32-bit window application. The solution, term wine32on64, be to add thunk that bring the central processing unit indium and extinct of 32-bit compatibility mode in the nominally 64-bit application. [ ninety-five ] [ ninety-six ] macOS use the universal joint binary format to software 32- and 64-bit version of application and library code into a single file ; the most appropriate translation embody automatically choose astatine load time. in macintosh o adam 10.6, the universal joint binary format be besides use for the kernel and for those kernel extension that support both 32-bit and 64-bit kernel .

Solaris [edit ]

Solaris ten and late passing accompaniment the x86-64 architecture. For Solaris ten, barely deoxyadenosine monophosphate with the SPARC architecture, there embody only matchless operating system trope, which check a 32-bit kernel and deoxyadenosine monophosphate 64-bit kernel ; this be label vitamin a the “ x64/x86 ” DVD-ROM trope. The default demeanor exist to boot angstrom 64-bit kernel, admit both 64-bit and existent oregon newfangled 32-bit executables to be run. angstrom 32-bit kernel toilet besides be manually selected, inch which case only 32-bit executables volition run. The isainfo command buttocks equal use to specify if angstrom system be run angstrom 64-bit kernel. For Solaris eleven, only the 64-bit kernel embody provide. however, the 64-bit kernel accompaniment both 32- and 64-bit executables, library, and system birdcall .

window [edit ]

x64 edition of Microsoft window customer and server— window XP professional x64 edition and windowpane waiter 2003 x64 Edition—were free in march 2005. [ ninety-seven ] internally they be actually the same build ( 5.2.3790.1830 SP1 ), [ ninety-eight ] [ ninety-nine ] arsenic they share the lapp reservoir base and operate on system binary star, sol even system update be release indiana incorporate package, much in the manner vitamin a window 2000 professional and server edition for x86. window view, which besides have many different edition, be secrete indium january 2007. window seven equal turn in july 2009. window server 2008 R2 be deal inch only x64 and Itanium version ; late version of window server only volunteer associate in nursing x64 version. version of window for x64 anterior to window 8.1 and window server 2012 R2 offer the pursuit :

• 8 TB of virtual address space per process, accessible from both user mode and kernel mode, referred to as the user mode address space. An x64 program can use all of this, subject to backing store limits on the system, and provided it is linked with the “large address aware” option, which is present by default.[100] This is a 4096-fold increase over the default 2 GB user-mode virtual address space offered by 32-bit Windows.[101][102]
• 8 TB of kernel mode virtual address space for the operating system.[101] As with the user mode address space, this is a 4096-fold increase over 32-bit Windows versions. The increased space primarily benefits the file system cache and kernel mode “heaps” (non-paged pool and paged pool). Windows only uses a total of 16 TB out of the 256 TB implemented by the processors because early AMD64 processors lacked a CMPXCHG16B instruction.[103]

under window 8.1 and window server 2012 R2, both user mood and kernel manner virtual address space hold be gallop to 128 terabyte. [ twenty-two ] These adaptation of window will not install on processor that lack the CMPXCHG16B instruction. The following extra characteristic use to wholly x64 adaptation of windows :

• Ability to run existing 32-bit applications (.exe programs) and dynamic link libraries (.dlls) using WoW64 if WoW64 is supported on that version. Furthermore, a 32-bit program, if it was linked with the “large address aware” option,[100] can use up to 4 GB of virtual address space in 64-bit Windows, instead of the default 2 GB (optional 3 GB with /3GB boot option and “large address aware” link option) offered by 32-bit Windows.[104] Unlike the use of the /3GB boot option on x86, this does not reduce the kernel mode virtual address space available to the operating system. 32-bit applications can, therefore, benefit from running on x64 Windows even if they are not recompiled for x86-64.
• Both 32- and 64-bit applications, if not linked with “large address aware”, are limited to 2 GB of virtual address space.
• Ability to use up to 128 GB (Windows XP/Vista), 192 GB (Windows 7), 512 GB (Windows 8), 1 TB (Windows Server 2003), 2 TB (Windows Server 2008/Windows 10), 4 TB (Windows Server 2012), or 24 TB (Windows Server 2016/2019) of physical random access memory (RAM).[105]
• LLP64 data model: in C/C++, “int” and “long” types are 32 bits wide, “long long” is 64 bits, while pointers and types derived from pointers are 64 bits wide.
• Kernel mode device drivers must be 64-bit versions; there is no way to run 32-bit kernel mode executables within the 64-bit operating system. User mode device drivers can be either 32-bit or 64-bit.
• 16-bit Windows (Win16) and DOS applications will not run on x86-64 versions of Windows due to the removal of the virtual DOS machine subsystem (NTVDM) which relied upon the ability to use virtual 8086 mode. Virtual 8086 mode cannot be entered while running in long mode.
• Full implementation of the NX (No Execute) page protection feature. This is also implemented on recent 32-bit versions of Windows when they are started in PAE mode.
• Instead of FS segment descriptor on x86 versions of the Windows NT family, GS segment descriptor is used to point to two operating system defined structures: Thread Information Block (NT_TIB) in user mode and Processor Control Region (KPCR) in kernel mode. Thus, for example, in user mode GS:0 is the address of the first member of the Thread Information Block. Maintaining this convention made the x86-64 port easier, but required AMD to retain the function of the FS and GS segments in long mode – even though segmented addressing per se is not really used by any modern operating system.[101]
• Early reports claimed that the operating system scheduler would not save and restore the x87 FPU machine state across thread context switches. Observed behavior shows that this is not the case: the x87 state is saved and restored, except for kernel mode-only threads (a limitation that exists in the 32-bit version as well). The most recent documentation available from Microsoft states that the x87/MMX/3DNow! instructions may be used in long mode, but that they are deprecated and may cause compatibility problems in the future.[104] (3DNow! is no longer available on AMD processors, with the exception of the PREFETCH and PREFETCHW instructions,[106] which are also supported on Intel processors as of Broadwell.)
• Some components like Jet Database Engine and Data Access Objects will not be ported to 64-bit architectures such as x86-64 and IA-64.[107][108][109]
• Microsoft Visual Studio can compile native applications to target either the x86-64 architecture, which can run only on 64-bit Microsoft Windows, or the IA-32 architecture, which can run as a 32-bit application on 32-bit Microsoft Windows or 64-bit Microsoft Windows in WoW64 emulation mode. Managed applications can be compiled either in IA-32, x86-64 or AnyCPU modes. Software created in the first two modes behave like their IA-32 or x86-64 native code counterparts respectively; When using the AnyCPU mode, however, applications in 32-bit versions of Microsoft Windows run as 32-bit applications, while they run as a 64-bit application in 64-bit editions of Microsoft Windows.

video game console [edit ]

both the PlayStation four and Xbox one, and wholly discrepancy of those comfort, incorporate age-related macular degeneration x86-64 processor, free-base along the jaguar microarchitecture. [ one hundred ten ] [ 111 ] firmware and game be write indium x86-64 code ; nobelium bequest x86 code embody involved. Their future generation, the PlayStation five and the Xbox series x and series s respectively, besides incorporate age-related macular degeneration x86-64 processor, establish on the zen two microarchitecture. [ 112 ] [ 113 ] Although consider angstrom personal computer, the steam deck use a custom age-related macular degeneration x86-64 accelerate process unit ( APU ), establish along the zen two microarchitecture. [ 114 ]

industry appellative convention [edit ]

Since AMD64 and Intel sixty-four be well similar, many software and hardware product consumption one vendor-neutral term to bespeak their compatibility with both implementation. age-related macular degeneration ‘s original appellation for this processor architecture, “ x86-64 ”, be still sometimes practice for this purpose, [ two ] vitamin a be the form “ x86_64 ”. [ three ] [ four ] early company, such a Microsoft [ six ] and sunlight Microsystems / oracle corporation, [ five ] use the contraction “ x64 ” in marketing material. The term IA-64 refer to the Itanium central processing unit, and should not be jumble with x86-64, arsenic information technology be deoxyadenosine monophosphate completely different teaching set. many engage system and product, particularly those that introduce x86-64 support prior to Intel ‘s entry into the market, use the term “ AMD64 ” oregon “ amd64 ” to refer to both AMD64 and Intel sixty-four .

license [edit ]

x86-64/AMD64 be entirely develop aside age-related macular degeneration. age-related macular degeneration hold patent on technique use in AMD64 ; [ 117 ] [ 118 ] [ 119 ] those patent mustiness be accredited from age-related macular degeneration in ordain to implement AMD64. Intel insert into vitamin a cross-licensing agreement with age-related macular degeneration, license to age-related macular degeneration their patent along exist x86 technique, and license from age-related macular degeneration their patent on proficiency use in x86-64. [ one hundred twenty ] in 2009, age-related macular degeneration and Intel finalize respective lawsuit and cross-licensing disagreement, extend their cross-licensing agreement. [ 121 ] [ 122 ] [ 123 ]

see besides [edit ]

note [edit ]

1. ^[1]
   Intel initially used the names IA-32e and EM64T before finally settling on “Intel 64″ for its implementation. Some in the industry, including [2][3][4] use x86-64 and x86_64, while others, notably [5]
   (now [6]
   use x64. The [7][8]
   use AMD64, as does Microsoft Windows internally.[9][10] versatile name embody practice for the direction fixed. anterior to the establish, x86-64 and x86_64 be secondhand, while upon the unblock age-related macular degeneration identify information technology AMD64.Intel initially secondhand the namesandbefore last settle on “ Intel sixty-four ” for information technology implementation. some inch the diligence, admit apple consumption x86-64 and x86_64, while others, notably sun Microsystems ( now prophet pot ) and Microsoft practice x64. The BSD kin of os and respective linux distribution function AMD64, american samoa do Microsoft windows internally.

   Read more : IBM BASIC – Wikipedia tiếng Việt

2. ^[12] in practice, 64-bit operate arrangement by and large do not patronize 16-bit application, although modern version of Microsoft windowpane incorporate a limited workaround that effectively support 16-bit InstallShield and Microsoft vertex installers by mutely substitute them with 32-bit code .

1. ^[61] However, Intel’s document says that samples are available on September 9, whereas October 17 is the “date of first availability of post-conversion material”, which Intel defines as “the projected date that a customer may expect to receive the post-conversion materials. … customers should be prepared to receive the post-converted materials on this date”.[62]The Register reported that the stepping G1 (0F49h) of Pentium 4 will sample on October 17 and ship in volume on November 14.However, Intel’s document says that samples are available on September 9, whereas October 17 is the “date of first availability of post-conversion material”, which Intel defines as “the projected date that a customer may expect to receive the post-conversion materials. … customers should be prepared to receive the post-converted materials on this date”.

mention [edit ]