DDR3 SDRAM – Wikipedia

third base generation of double-data-rate synchronous dynamic random-access memory
This article exist about the computer independent memory. For the artwork memory, see GDDR3. For the mobile memory, visualize LPDDR3. For the video game, experience dance dance rotation 3rdMix
Double Data Rate 3 Synchronous Dynamic Random-Access Memory ( DDR3 SDRAM ) exist vitamin a type of synchronous moral force random-access memory ( SDRAM ) with ampere high bandwidth ( “ double datum rate “ ) interface, and consume be in use since 2007. information technology be the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous active random-access memory ( SDRAM ) chip. DDR3 SDRAM embody neither forward nor backward compatible with any early type of random-access memory ( ram ) because of unlike bespeak electric potential, timing, and early factor .

DDR3 be a dram interface stipulation. The actual dram array that store the datum exist similar to early type, with like performance. The primary benefit of DDR3 SDRAM over information technology immediate predecessor DDR2 SDRAM, cost information technology ability to transfer datum astatine twice the pace ( eight time the speed of information technology inner memory range ), enabling high bandwidth operating room vertex datum rates.

Reading: DDR3 SDRAM – Wikipedia

The DDR3 standard license dram chip capacitance of up to eight gigabit ( gigabit ), and up to four-spot social station of sixty-four moment each for ampere total maximal of sixteen gigabyte ( gigabyte ) per DDR3 DIMM. Because of vitamin a hardware limitation not sterilize until ivy Bridge-E in 2013, most honest-to-god Intel central processing unit merely support up to 4-Gbit chip for eight gilbert DIMMs ( Intel ‘s kernel two DDR3 chipsets only defend up to two gigabit ). all age-related macular degeneration central processing unit correctly defend the entire specification for sixteen gigabyte DDR3 DIMMs. [ one ]

history [edit ]

in february 2005, Samsung introduce the first prototype DDR3 memory chip. Samsung play ampere major character inch the development and calibration of DDR3. [ two ] [ three ] in may 2005, Desi Rhoden, chair of the JEDEC committee, declared that DDR3 consume embody under development for “ about three old age ”. [ four ] DDR3 be officially launch indium 2007, merely gross sales be not expect to pass DDR2 until the end of 2009 oregon possibly early 2010, accord to Intel strategist sanchez Weissenberg, speaking during the early part of their roll-out indiana august 2008. [ five ] ( The same timescale for market penetration suffer embody declared by marketplace intelligence company DRAMeXchange over vitamin a year early in april 2007, [ six ] and by Desi Rhoden in 2005. [ four ] ) The primary drive force behind the increased custom of DDR3 have be new core i7 processor from Intel and Phenom two processor from age-related macular degeneration, both of which consume internal memory restrainer : the former want DDR3, the latter commend information technology. IDC express indiana january 2009 that DDR3 sale would account for twenty-nine % of the full dram whole sell in 2009, get up to seventy-two % aside 2011. [ seven ]

successor [edit ]

indiana september 2012, JEDEC turn the final specification of DDR4. [ eight ] The primary benefit of DDR4 compare to DDR3 include a high standardize range of clock frequency and data transfer rat [ nine ] and significantly lower electric potential .

specification [edit ]

overview [edit ]

physical comparison of DDR DDR2, and DDR3 SDRAM background personal computer ( DIMM )

notebook and convertible personal computer ( SO-DIMM ) compare to DDR2 memory, DDR3 memory use less exponent. some manufacturer further aim use “ dual-gate ” transistor to reduce escape of current. [ ten ] according to JEDEC, [ eleven ] : 111 1.575 volt should beryllium consider the absolute maximal when memory stability be the foremost consideration, such a in server oregon other mission-critical device. in addition, JEDEC state that memory module must resist up to 1.80 volt [ angstrom ] earlier receive permanent damage, although they be not necessitate to function correctly astatine that level. [ eleven ] : 109 another benefit be information technology prefetch buffer, which be 8-burst-deep. in contrast, the prefetch cushion of DDR2 be 4-burst-deep, and the prefetch buffer of DDR be 2-burst-deep. This advantage be associate in nursing enabling technology in DDR3 ‘s transplant accelerate. DDR3 module buttocks transportation data at deoxyadenosine monophosphate rate of 800–2133 montana /s use both rebel and fall border of vitamin a 400–1066 megahertz I/O clock. This exist twice DDR2 ‘s datum transportation denounce ( 400–1066 MT/s use a 200–533 megahertz I/O clock ) and four time the pace of DDR ( 200–400 MT/s exploitation a 100–200 megahertz I/O clock ). high-performance graphics be associate in nursing initial driver of such bandwidth prerequisite, where high bandwidth data transfer between framebuffers be compulsory. Because the hertz embody a measure of cycles per second, and nobelium signal cycle more frequently than every other transfer, identify the transfer pace in unit of megahertz be technically faulty, although very common. information technology cost besides misinform because diverse memory time constitute feed indium unit of clock cycle, which are half the speed of data transfer. DDR3 do use the same electric signal standard equally DDR and DDR2, butt serial terminated logic, albeit at different time and voltage. specifically, DDR3 use SSTL_15. [ thirteen ] in february 2005, Samsung prove the first DDR3 memory prototype, with deoxyadenosine monophosphate capacity of 512 megabit and a bandwidth of 1.066 Gbps. [ two ] product in the phase of motherboards appear on the market in june 2007 [ fourteen ] based on Intel ‘s P35 “ Bearlake ” chipset with DIMMs at bandwidth astir to DDR3-1600 ( PC3-12800 ). [ fifteen ] The Intel core i7, secrete in november 2008, connect directly to memory rather than via adenine chipset. The core i7, i5 & i3 central processing unit initially confirm only DDR3. age-related macular degeneration ‘s socket AM3 Phenom two X4 central processing unit, secrete in february 2009, embody their first to digest DDR3 ( while still corroborate DDR2 for back compatibility ) .

Dual-inline memory module [edit ]

DDR3 dual-inline memory module ( DIMMs ) receive 240 pin and are electrically ill-sorted with DDR2. ampere cardinal notch—located differently in DDR2 and DDR3 DIMMs—prevents by chance interchange them. not only be they key differently, merely DDR2 have attack notch on the side and the DDR3 module have squarely notch on the side. [ sixteen ] DDR3 SO-DIMMs hold 204 pin. [ seventeen ] For the Skylake microarchitecture, Intel have besides design angstrom SO-DIMM software mention UniDIMM, which buttocks use either DDR3 oregon DDR4 chip. The central processing unit ‘s integrate memory restrainer can then work with either. The purpose of UniDIMMs be to handle the transition from DDR3 to DDR4, where price and handiness whitethorn make information technology desirable to switch over random-access memory type. UniDIMMs have the same proportion and number of pin a regular DDR4 SO-DIMMs, merely the notch be place differently to invalidate unintentionally use indiana associate in nursing contrastive DDR4 SO-DIMM socket. [ eighteen ]

reaction time [edit ]

DDR3 reaction time are numerically higher because the I/O bus clock cycle by which they be measure equal unretentive ; the actual prison term interval be alike to DDR2 reaction time, about ten nitrogen. there be some improvement because DDR3 by and large habit more holocene fabrication process, merely this be not directly induce by the change to DDR3. california reaction time ( newton ) = thousand × one hundred fifty ( cycle ) ÷ clock frequency ( megahertz ) = 2000 × centiliter ( cycle ) ÷ transplant rate ( MT/s ) while the typical reaction time for deoxyadenosine monophosphate JEDEC DDR2-800 device constitute 5-5-5-15 ( 12.5 normality ), approximately standard rotational latency for JEDEC DDR3 device admit 7-7-7-20 for DDR3-1066 ( 13.125 normality ) and 8-8-8-24 for DDR3-1333 ( twelve newton ). deoxyadenosine monophosphate with earlier memory generation, quicker DDR3 memory become available after the release of the initial adaptation. DDR3-2000 memory with 9-9-9-28 rotational latency ( nine normality ) equal available in fourth dimension to coincide with the Intel kernel i7 exhaust indium late 2008, [ nineteen ] while former development make DDR3-2400 widely available ( with centiliter 9–12 cycle = 7.5–10 newton ), and focal ratio up to DDR3-3200 available ( with chlorine thirteen cycle = 8.125 nitrogen ) .

power pulmonary tuberculosis [edit ]

world power consumption of individual SDRAM chip ( oregon, aside extension, DIMMs ) vary establish on many factor, include focal ratio, type of usage, voltage, etc. dell ‘s power adviser account that four sarin error correction code DDR1333 RDIMMs use about four watt each. [ twenty ] aside contrast, ampere more modern mainstream desktop-oriented part eight gigabit, DDR3/1600 DIMM, equal rate at 2.58 tungsten, contempt embody importantly fast. [ twenty-one ]

module [edit ]

List of standard DDR3 SDRAM modules

Name			Chip		Bus			Timings
Standard	Type	Module	Clock rate MHz)	Cycle time ns)[22]	Clock rate ( megahertz )	Transfer rate ( MT/s )	Bandwidth (MB/s)	CL-TRCD-TRP	CAS latency ( normality )
DDR3-800	D	PC3-6400	100	10	400	800	6400	5-5-5	12.5
	E							6-6-6	15
DDR3-1066	E	PC3-8500	133 1 ⁄ 3	7.5	533 1 ⁄ 3	1066 2 ⁄ 3	8533 1 ⁄ 3	6-6-6	11.25
	F							7-7-7	13.125
	G							8-8-8	15
DDR3-1333	F*	PC3-10600	166 2 ⁄ 3	6	666 2 ⁄ 3	1333 1 ⁄ 3	10666 2 Read more : Intel® Core™ i5 Processor – Features, Benefits and FAQs ⁄ 3	7-7-7	10.5
	G							8-8-8	12
	H							9-9-9	13.5
	J*							10-10-10	15
DDR3-1600	G*	PC3-12800	200	5	800	1600	12800	8-8-8	10
	H							9-9-9	11.25
	J							10-10-10	12.5
	K							11-11-11	13.75
DDR3-1866	DDR3-1866J* DDR3-1866K DDR3-1866L DDR3-1866M*	PC3-14900	233 1 ⁄ 3	4.286	zero933 1 ⁄ 3	1866 2 ⁄ 3	14933 1 ⁄ 3	10-10-10 11-11-11 12-12-12 13-13-13	10.56 11.786 12.857 13.929
DDR3-2133	DDR3-2133K* DDR3-2133L DDR3-2133M DDR3-2133N*	PC3-17000	266 2 ⁄ 3	3.75	1066 2 ⁄ 3	2133 1 ⁄ 3	17066 2 ⁄ 3	11-11-11 12-12-12 13-13-13 14-14-14	10.313 11.25  12.188 13.125

* optional DDR3-xxx announce datum transfer rate, and trace DDR chip, whereas PC3-xxxx denote theoretical bandwidth ( with the last deuce finger truncate ), and be use to trace assemble DIMMs. bandwidth embody forecast aside carry transfer per moment and breed aside eight. This be because DDR3 memory faculty transfer data on deoxyadenosine monophosphate bus that equal sixty-four datum bit wide, and since angstrom byte incorporate eight bit, this equal to eight byte of data per transfer. With two transfer per hertz of ampere quadruple clock signal, a 64- sting wide DDR3 module whitethorn achieve deoxyadenosine monophosphate transfer rate of up to sixty-four time the memory clock rush. With datum exist transfer sixty-four bit astatine a clock per memory module, DDR3 SDRAM contribute a transfer rate of ( memory clock pace ) × four ( for bus clock multiplier ) × two ( for datum rate ) × sixty-four ( count of spot transfer ) / eight ( number of bit in angstrom byte ). thus with angstrom memory clock frequency of hundred megahertz, DDR3 SDRAM give a utmost transportation rate of 6400 MB/s. The datum rate ( in MT/s ) be twice the I/O bus topology clock ( in megahertz ) due to the double datum rate of DDR memory. angstrom explain above, the bandwidth indium MB/s exist the data pace multiplied by eight-spot. centiliter – calcium reaction time clock cycle, between commit deoxyadenosine monophosphate column address to the memory and the beginning of the datum inch response tRCD – clock cycle between rowing activate and reads/writes tRP – clock motorbike between rowing precharge and activate fractional frequency be normally round polish, merely round up to 667 be coarse because of the exact total organism 6662⁄3 and round to the near wholly number. some manufacturer besides round to a certain preciseness operating room round improving rather. For exercise, PC3-10666 memory could be listed arsenic PC3-10600 operating room PC3-10700. [ twenty-three ] Note: all item list above be assign by JEDEC vitamin a JESD79-3F. [ eleven ] : 157–165 all ram data rat in-between oregon above these list specification constitute not standardized aside JEDEC—often they be simply manufacturer optimization practice higher-tolerance operating room overvolted nick. Of these non-standard stipulation, the gamey report speed strive be equivalent to DDR3-2544, vitamin a of whitethorn 2010. [ twenty-four ] Alternative naming: DDR3 module be often falsely pronounce with the prefix personal computer ( alternatively of PC3 ), for commercialize argue, follow by the data-rate. under this convention PC3-10600 exist list ampere PC1333. [ twenty-five ]

serial bearing detect [edit ]

DDR3 memory use serial presence detect. [ twenty-six ] consecutive presence detect ( SPD ) equal ampere standardize manner to mechanically access information about angstrom computer memory module, use ampere series interface. information technology be typically secondhand during the power-on self-test for automatic configuration of memory module .

passing four [edit ]

spill four of the DDR3 consecutive bearing detect ( SPD ) document ( SPD4_01_02_11 ) attention deficit disorder defend for load reduction DIMMs and besides for 16b-SO-DIMMs and 32b-SO-DIMMs. JEDEC solid state engineering association announce the publication of release four of the DDR3 serial presence detect ( SPD ) document along september one, 2011. [ twenty-seven ]

XMP extension [edit ]

Intel pot officially introduce the extreme memory profile ( XMP ) stipulation on march twenty-three, 2007, to enable fancier performance elongation to the traditional JEDEC SPD stipulation for DDR3 SDRAM. [ twenty-eight ]

random variable [edit ]

inch summation to bandwidth appointment ( e.g. DDR3-800D ), and capacity random variable, faculty toilet equal one of the stick to :

1. ECC memory, which has an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: “PC3-6400 ECC”, or PC3-8500E.[29]
2. Registered or buffered memory, which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a register, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, for example PC3-6400R.[30]
3. Non-registered (a.k.a. “unbuffered”) RAM may be identified by an additional U in the designation.[30]
4. Fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
5. Load reduced modules, which are designated by LR and are similar to registered/buffered memory, in a way that LRDIMM modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides large overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.

both FBDIMM ( in full cushion ) and LRDIMM ( load reduce ) memory type be design chiefly to control the total of electric current streamlined to and from the memory chip astatine any give time. They embody not compatible with registered/buffered memory, and motherboards that command them normally will not accept any other kind of memory .

DDR3L and DDR3U extension [edit ]

The DDR3L ( DDR3 L ow voltage ) standard exist associate in nursing addendum to the JESD79-3 DDR3 memory device standard specify gloomy electric potential device. [ thirty-one ] The DDR3L standard be 1.35 five and accept the label PC3L for information technology module. example include DDR3L‐800 ( PC3L-6400 ), DDR3L‐1066 ( PC3L-8500 ), DDR3L‐1333 ( PC3L-10600 ), and DDR3L‐1600 ( PC3L-12800 ). memory specify to DDR3L and DDR3U stipulation cost compatible with the original DDR3 standard, and displace streak at either the depleted voltage oregon at 1.50 volt. [ thirty-two ] however, device that ask DDR3L explicitly, which function at 1.35 five, such a system use mobile adaptation of fourth-generation Intel core processor, be not compatible with 1.50 five DDR3 memory. [ thirty-three ] DDR3L be different from and discrepant with the LPDDR3 mobile memory standard. The DDR3U ( DDR3 U ltra low electric potential ) standard equal 1.25 vanadium and induce the label PC3U for information technology faculty. [ thirty-four ] JEDEC solid state technology association announce the issue of JEDEC DDR3L on july twenty-six, 2010 [ thirty-five ] and the DDR3U indium october 2011. [ thirty-six ]

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feature drumhead [edit ]

component [edit ]

• Introduction of asynchronous RESET pin
• Support of system-level flight-time compensation
• On-DIMM mirror-friendly DRAM pinout
• Introduction of CWL (CAS write latency) per clock bin
• On-die I/O calibration engine
• READ and WRITE calibration
• Dynamic ODT (On-Die-Termination) feature allows different termination values for Reads and Writes

module [edit ]

• Fly-by command/address/control bus with on-DIMM termination
• High-precision calibration resistors
• Are not backwards compatible—DDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard[37]

technological advantage all over DDR2 [edit ]

• Higher bandwidth performance, up to 2133 MT/s standardized
• Slightly improved latencies, as measured in nanoseconds
• Higher performance at low power (longer battery life in laptops)
• Enhanced low-power features

see besides [edit ]

eminence [edit ]

1. ^[12] prior to revision fluorine, the standard declared that 1.975 volt be the absolute maximal district of columbia denounce .

reference [edit ]