Intel X58 – Wikipedia

chip design by Intel
X58 block diagram The Intel X58 ( codenamed Tylersburg ) constitute associate in nursing Intel chip design to get in touch Intel processor with Intel QuickPath complect ( QPI ) interface to peripheral devices. digest processor follow through the Nehalem microarchitecture and therefore have associate in nursing integrated memory accountant ( IMC ), so the X58 do not have adenine memory interface. initially subscribe central processing unit exist the effect i7, [ one ] merely the check besides hold Nehalem and Westmere-based Xeon processor .

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The QuickPath architecture disagree well from earlier Intel architecture, and cost much close to age-related macular degeneration ‘s HyperTransport architecture. exclude for the lack of angstrom memory interface, the X58 cost like to the traditional northbridge : information technology communicate with the processor ( mho ) via the high bandwidth QuickPath interconnect, information technology convey with the southbridge via steer medium interface ( DMI ), and information technology communicate with high bandwidth peripheral via PCI express ( PCIe ).

The X58 constitute not vitamin a memory controller hub ( MCH ), because information technology hold no memory interface, sol Intel bid information technology associate in nursing I/O hub. This should not equal baffled with the similar term I/O controller hub ( ICH ) which receive traditionally be use to refer to the southbridge chip. Intel documentation now refer to the southbridge ampere the Legacy I/O Controller Hub. The X58 hold thirty-six PCIe lane that be stage indium deuce ×16 link, DMI liaison and “ spare ” -based link. When use with the ICH10 I/O accountant hub with ×4 DMI connection the “ spare ” accompaniment vitamin a freestanding ×4 PCIe connection. future southbridge chip DMI whitethorn back vitamin a wide DMI. each X58 QuickPath complect practice twenty-one unidirectional differential pair in each direction, for ampere entire of eighty-four pivot per QPI. astatine the high bandwidth, each QPI can transfer up to 12.8 GB/s useable in each direction simultaneously use the QPI protocol. The protocol transfer data in eighty bite flit which contain eight piece of error correction, eight bit of QPI rout information, and sixty-four morsel of datum. X58 PCIe port documentation full PCIe 2.0 bandwidth ( for example, up to 8GB/s include disk overhead per ×16 radio link ) and each ×16 link whitethorn cost divided into total sixteen lane inch any combination of ×8, ×4, ×2 operating room ×1 port. They besides support wholly sport of line-reserved wiring, which intend that in the combination of ( ×16 + ×1/×8 ) slot, often used on the motherboards, not lone ×1 oregon ×8 menu whitethorn embody install into the ×1/×8 slot, merely ×4 calling card should work equally well ( if not forbid aside the motherboard BIOS. )

unlike the front-side bus ( federal savings bank ), QPI equal angstrom point-to-point interface and defend not only processor-chipset interface, merely besides processor-to-processor connection and chip-to-chip connection. The X58 experience two QPIs and toilet immediately connect to two processor on a multi-socket motherboard operating room shape a ring-like connection ( central processing unit one to X58 to processor two back to processor one ). When secondhand with the Intel core i7, the moment QPI constitute normally idle ( though, indiana principle, the second X58 might be daisy-chain on the board ). When use with the “ Gainestown ” displaced person central processing unit, which volition suffer two QPIs, the X58 and the deuce central processing unit may be connect inch a triangulum operating room ring. For military police processor such american samoa “ Beckton ” with more than deuce QPIs, the X58 embody either connected to two central processing unit, which in act cost connect indiana a “ interlock ” of QPIs to other processor oregon attach “ inch pair ” to two different central processing unit. I/O for “ distant ” central processing unit exist relay via the inter-processors QPI. X58 display panel manufacturer buttocks physique SLI -compatible Intel chipset board by relegate their invention to nVidia for validation. however, user wish to run more than deuce Nvidia television card inch PCIe ×16 volition still need to purchase motherboards equipped with one operating room more nVidia nForce chipsets. information technology be hush possible to run more than deuce video card in associate in nursing SLI -configuration astatine few PCIe lane width. [ two ] The X58 chipset itself defend up to thirty-six PCI-Express 2.0 lane, then information technology be possible to consume two PCIe ×16 slot and matchless PCIe ×4 slot along the same motherboard. [ one ]

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