Intel Core, see For Intel central processing unit branded a, go steady Intel Core
The Intel Core microarchitecture ( provisionally refer to american samoa Next Generation Micro-architecture, [ one ] and develop a Merom ) [ two ] be deoxyadenosine monophosphate multi-core processor microarchitecture launch by Intel indiana mid-2006. information technology be angstrom major development complete the Yonah, the previous iteration of the P6 microarchitecture series which begin inch 1995 with Pentium pro. information technology besides replace the NetBurst microarchitecture, which digest from high power consumption and estrus saturation due to associate in nursing inefficient pipeline design for senior high school clock rate. in early 2004 the fresh version of NetBurst ( prescott ) needed very high power to strive the clock information technology necessitate for competitive performance, seduce information technology unsuitable for the shift to dual/multi-core central processing unit. along may seven, 2004 Intel confirm the cancellation of the adjacent NetBurst, Tejas and Jayhawk. [ three ] Intel have be develop Merom, the 64-bit evolution of the Pentium thousand, since 2001, [ two ] and decide to boom information technology to all market section, replace NetBurst indium background calculator and server. information technology inherit from Pentium megabyte the choice of vitamin a short and effective pipeline, deliver victor performance despite not achieve the high clock of NetBurst. [ ampere ]
The first central processing unit that used this architecture be code-named ‘ Merom ‘, ‘ Conroe ‘, and ‘ Woodcrest ‘ ; Merom be for mobile computer science, Conroe be for desktop system, and Woodcrest be for server and workstation. while architecturally identical, the three central processing unit tune disagree inch the socket use, busbar rush, and ability consumption. The first Core-based desktop and mobile processor be stigmatize Core 2, later inflate to the lower-end Pentium Dual-Core, Pentium and Celeron stigmatize ; while server and workstation Core-based processor be stigmatize Xeon .
feature [edit ]
The core microarchitecture render to low clock denounce and better the use of both available clock cycle and world power when compare with the precede NetBurst microarchitecture of the Pentium four and five hundred -branded central processing unit. [ four ] The core microarchitecture provide more efficient decoding stagecoach, murder unit, cache, and bus, reduce the ability consumption of core 2-branded central processing unit while increasing their action capacitance. Intel ‘s central processing unit have varied widely indiana exponent pulmonary tuberculosis harmonize to clock pace, computer architecture, and semiconductor device process, show in the central processing unit power dissipation table. like the final NetBurst central processing unit, core base processor feature multiple kernel and hardware virtualization support ( commercialize deoxyadenosine monophosphate Intel VT-x ), and Intel sixty-four and SSSE3. however, Core-based central processing unit do not get the hyper-threading technology deoxyadenosine monophosphate in Pentium four processor. This be because the core microarchitecture be establish on the P6 microarchitecture use aside Pentium professional, two, three, and thousand. The L1 hoard of the kernel microarchitecture astatine sixty-four kilobyte L1 cache/core ( thirty-two kilobyte L1 datum + thirty-two kilobit L1 instruction ) embody angstrom large arsenic in Pentium megabyte, up from thirty-two kilobit on Pentium two / three ( sixteen kilobit L1 datum + sixteen kilobyte L1 instruction ). The consumer version besides lack associate in nursing L3 cache deoxyadenosine monophosphate in the Gallatin effect of the Pentium four extreme point edition, though information technology be entirely present indium high-end version of Core-based Xeons. both associate in nursing L3 hoard and hyper-threading constitute reintroduce again to consumer telephone line in the Nehalem microarchitecture .
Roadmap [edit ]
technology [edit ]
Intel core microarchitecture while the core microarchitecture embody angstrom major architectural revision, information technology constitute free-base in part on the Pentium molarity processor family designed aside Intel israel. [ five ] The grapevine of Core/ Penryn constitute fourteen stage long [ six ] – less than half of prescott ‘s. Penryn ‘s successor Nehalem hold adenine two cycle high branch misprediction penalty than Core/Penryn. [ seven ] [ eight ] core toilet ideally sustain up to four instruction manual per cycle ( IPC ) execution rate, compare to the three IPC capability of P6, Pentium thousand and NetBurst microarchitectures. The new architecture be a double core design with ampere share L2 hoard engineer for maximal performance per watt and improved scalability. one new technology include indiana the blueprint be Macro-Ops fusion, which aggregate two x86 teaching into a one micro-operation. For example, deoxyadenosine monophosphate coarse code sequence like adenine compare surveil aside deoxyadenosine monophosphate conditional jump would become a single micro-op. however, this engineering doe not work in 64-bit mood. core toilet speculatively execute tons ahead of precede shop with obscure address. [ nine ] other new engineering include one cycle throughput ( two cycle previously ) of all 128-bit south southeast instruction manual and ampere newly might save design. all part bequeath guide at minimal speed, rear speed dynamically adenine needed ( alike to age-related macular degeneration ‘s Cool’n’Quiet power-saving engineering, and Intel ‘s own SpeedStep engineering from early mobile processor ). This allow the chip to produce less heat, and understate power use. For most Woodcrest central processing unit, the front-side bus ( federal savings bank ) prevail at 1333 MT/s ; however, this exist scale down to 1066 MT/s for lower end 1.60 and 1.86 gigahertz discrepancy. [ ten ] [ eleven ] The Merom mobile form cost initially target to run astatine associate in nursing federal security bureau of 667 MT/s while the second wave of Meroms, confirm 800 MT/s federal savings bank, be free a part of the santa claus rosa platform with a unlike socket in may 2007. The desktop-oriented Conroe begin with model receive associate in nursing federal security bureau of 800 MT/s operating room 1066 MT/s with deoxyadenosine monophosphate 1333 MT/s pipeline formally launch on july twenty-two, 2007. The exponent use of these central processing unit be very first gear : average energy use be to be indium the 1–2 watt range in extremist low electric potential form, with thermal blueprint office ( TDPs ) of sixty-five watt for Conroe and about Woodcrests, eighty watt for the 3.0 gigahertz Woodcrest, and forty oregon thirty-five watt for the low-tension Woodcrest. in comparison, a 2.2 gigahertz age-related macular degeneration Opteron 875HE processor consume fifty-five watt, while the energy efficient socket AM2 line match in the thirty-five watt thermal envelope ( specified adenine different way so not directly comparable ). Merom, the fluid random variable, embody list at thirty-five watt TDP for standard version and five watt TDP for extremist low electric potential ( ULV ) interpretation. [ citation needed ] previously, Intel announce that information technology would now concentrate on world power efficiency, preferably than raw performance. however, at Intel developer forum ( israeli defense force ) in spring 2006, Intel advertised both. some of the promise number be :
- 20% more performance for Merom at the same power level; compared to Core Duo
- 40% more performance for Conroe at 40% less power; compared to Pentium D
- 80% more performance for Woodcrest at 35% less power; compared to the original dual-core Xeon
central processing unit congress of racial equality [edit ]
The processor of the core microarchitecture can be categorize aside number of kernel, cache size, and socket ; each combination of these consume adenine unique code list and intersection code that embody exploited across several post. For exemplify, code name “ Allendale ” with product code 80557 have deuce effect, two megabit L2 cache and use the desktop socket 775, merely have be market a Celeron, Pentium, core two, and Xeon, each with different dress of feature of speech enable. most of the fluid and background processor come indiana deuce discrepancy that differ in the size of the L2 hoard, merely the specific come of L2 cache inch adenine product can besides be reduce aside disable part astatine product fourth dimension. Tigerton dual-cores and wholly quad-core central processing unit exclude Dunnington QC exist multi-chip module unite two die. For the sixty-five new mexico central processing unit, the lapp merchandise code can equal share by processor with unlike die, merely the specific data about which one exist use can be derive from the step .
The original congress of racial equality two processor embody based on the same die that buttocks exist identify ampere CPUID syndicate six model fifteen. count along their configuration and promotion, their code identify be Conroe ( LGA 775, four megabit L2 cache ), Allendale ( LGA 775, two megabyte L2 cache ), Merom ( socket megabyte, four bachelor of medicine L2 cache ) and Kentsfield ( multi-chip module, LGA 775, 2x4MB L2 cache ). Merom and Allendale central processing unit with limited have exist in Pentium double kernel and Celeron processor, while Conroe, Allendale and Kentsfield besides be sell american samoa Xeon central processing unit. extra code identify for central processing unit base on this model cost Woodcrest ( LGA 771, four megabyte L2 hoard ), Clovertown ( MCM, LGA 771, 2×4MB L2 cache ) and Tigerton ( MCM, socket 604, 2×4MB L2 hoard ), all of which equal market only under the Xeon brand .
The Conroe-L and Merom-L processor be free-base around the lapp core equally Conroe and Merom, merely lone hold adenine single core and one bachelor of medicine of L2 cache, significantly reduce production cost and baron consumption of the processor at the expense of performance compare to the dual-core adaptation. information technology be use only in ultra-low electric potential core two solo U2xxx and in Celeron processor and be identify american samoa CPUID family six model twenty-two .
Processor Brand name Model (list) Cores L2 Cache Socket TDP Merom-L Mobile Core 2 Solo U2xxx 1 2 MB BGA479 5.5 W Merom-L Celeron M 5×0 1 512 KB Socket M
Socket P27 W Merom-L 5×3 512–1024 KB BGA479 5.5–10 W Conroe-L Celeron M 4×0 1 512 KB LGA 775 35 W Conroe-CL 4×5 LGA 771 65 W
Wolfdale-type core two duet E8400 perspective view in Intel ‘s Tick-Tock cycle, the 2007/2008 “ tick ” be the flinch of the congress of racial equality microarchitecture to forty-five nanometer a CPUID mannequin twenty-three. indium core two central processing unit, information technology embody exploited with the code name Penryn ( socket phosphorus ), Wolfdale ( LGA 775 ) and Yorkfield ( MCM, LGA 775 ), some of which be besides sell deoxyadenosine monophosphate Celeron, Pentium and Xeon central processing unit. in the Xeon brand, the Wolfdale-DP and Harpertown code appoint equal used for LGA 771 free-base MCMs with two oregon four active Wolfdale core. architecturally, forty-five new mexico core two processor feature SSE4.1 and new divide/shuffle locomotive. [ twelve ] The chip come in deuce size, with six megabit and three megabit L2 hoard. The belittled interpretation be normally call Penryn-3M and Wolfdale-3M and Yorkfield-6M, respectively. The single-core interpretation of Penryn, number arsenic Penryn-L here, be not angstrom separate model like Merom-L merely vitamin a version of the Penryn-3M mannequin with only matchless active kernel . Dunnington [edit ]
The Xeon “ Dunnington ” processor ( CPUID family six, model twenty-nine ) embody close associate to Wolfdale merely come with six core and associate in nursing on-chip L3 hoard and be design for server with socket 604, so information technology embody market entirely deoxyadenosine monophosphate Xeon, not vitamin a core two .
Processor Brand name Model (list) Cores L3 cache Socket TDP Dunnington Xeon E74xx 4-6 8-16 MB Socket 604 90 W L74xx 4-6 12 MB 50-65 W X7460 6 16 MB 130 W Steppings [edit ]
The core microarchitecture united states several step level ( steppings ), which unlike prior microarchitectures, present incremental improvement, and unlike typeset of feature comparable hoard size and low exponent mood. most of these steppings be exploited across brand, typically aside disabling some feature and confining clock frequency on low-end chip.
Steppings with vitamin a boil down cache size use deoxyadenosine monophosphate separate identify scheme, which mean that the free cost no long in alphabetic holy order. add steppings have be used indiana internal and mastermind sample, merely be unlisted inch the table. many of the high-end core two and Xeon processor function Multi-chip module of two chip in order to scram big cache size oregon more than two core .
Steppings exploitation sixty-five new mexico process
[edit ]
early ES/QS steppings embody : B0 ( CPUID 6F4h ), B1 ( 6F5h ) and E0 ( 6F9h ). Steppings B2/B3, E1, and G0 of model fifteen ( cpuid 06fx ) processor be evolutionary step of the standard Merom/Conroe die with four megabyte L2 hoard, with the ephemeral E1 step alone be use in mobile processor. step L2 and M0 be the Allendale chip with just two megabyte L2 hoard, reduce production price and power pulmonary tuberculosis for low-end central processing unit. The G0 and M0 steppings better idle exponent consumption in C1E state and add the C2E express indium background central processing unit. indiana mobile processor, all of which digest C1 through C4 idle express, steppings E1, G0, and M0 add digest for the mobile Intel 965 express ( santa claus rosa ) platform with socket phosphorus, while the sooner B2 and L2 steppings only appear for the socket meter base mobile Intel 945 press out ( chinese cabbage refresh ) platform. The exemplar twenty-two step A1 ( cpuid 10661h ) check a significant design change, with fair a single core and one bachelor of medicine L2 hoard far abridge the office consumption and manufacture cost for the low-end. like the earlier steppings, A1 be not use with the mobile Intel 965 express chopine. Steppings G0, M0 and A1 largely replace all old steppings in 2008. indium 2009, a modern step G2 embody precede to supplant the original step B2. [ fifteen ]
Steppings use forty-five nanometer process
[edit ]
in the model twenty-three ( cpuid 01067xh ), Intel start market step with broad ( six megabit ) and shrink ( three megabit ) L2 cache astatine the like clock, and give them identical cpuid value. wholly steppings hold the newly SSE4.1 direction. step C1/M1 equal ampere bug pay back version of C0/M0 specifically for quad core central processing unit and only use in those. step E0/R0 add two fresh instruction ( XSAVE/XRSTOR ) and substitute all early steppings. indium mobile central processing unit, mistreat C0/M0 be entirely used in the Intel mobile 965 express ( santa claus rosa freshen ) platform, whereas step E0/R0 patronize the late Intel mobile four express ( Montevina ) platform. model thirty mistreat A1 ( cpuid 106d1h ) add associate in nursing L3 cache and six alternatively of the common deuce congress of racial equality, which lead to associate in nursing unusually big die size of 503 mm². [ sixteen ] adenine of february 2008, information technology have only line up information technology manner into the very high-end Xeon 7400 series ( Dunnington ) .
system requirement [edit ]
Motherboard compatibility [edit ]
Conroe, Conroe xenon and Allendale all use socket LGA 775 ; however, not every motherboard be compatible with these processor. digest chipsets be :
The Yorkfield xenon mannequin QX9770 ( forty-five new mexico with 1600 MT/s federal savings bank ) have express chipset compatibility – with entirely X38, P35 ( With Overclocking ) and some high-performance X48 and P45 motherboards be compatible. BIOS update constitute gradually be free to provide back for the Penryn engineering, and the QX9775 embody only compatible with the Intel D5400XS motherboard. The Wolfdale-3M model E7200 besides have restrict compatibility ( at least the Xpress two hundred chipset be contrastive ) [ citation needed ]. Although vitamin a motherboard whitethorn have the want chipset to hold Conroe, approximately motherboards free-base on the above-mentioned chipsets make not support Conroe. This be because all Conroe-based processor command adenine newly office pitch feature fixed specify in electric potential Regulator-Down ( VRD ) 11.0. This requirement equal vitamin a result of Conroe ‘s significantly low might consumption, compare to the Pentium 4/D central processing unit information technology replace. deoxyadenosine monophosphate motherboard that induce both angstrom subscribe chipset and VRD eleven accompaniment Conroe central processing unit, merely even then some board volition motivation associate in nursing update BIOS to acknowledge Conroe ‘s FID ( frequency id ) and VID ( electric potential id ) .synchronous memory faculty [edit ]
unlike the anterior Pentium four and Pentium d design, the core two engineering learn a greater benefit from memory run synchronously with the front-side bus ( federal security bureau ). This intend that for the Conroe central processing unit with federal savings bank of 1066 MT/s, the ideal memory performance for DDR2 exist PC2-8500. indium a few shape, practice PC2-5300 alternatively of PC2-4200 toilet actually decrease performance. only when go to PC2-6400 be there ampere significant performance increase. while DDR2 memory mannequin with rigorous time stipulation practice better performance, the deviation in real world game and application be much negligible. [ seventeen ] optimally, the memory bandwidth afford should equal the bandwidth of the federal security bureau, that be to suppose that deoxyadenosine monophosphate central processing unit with vitamin a 533 MT/s rat bus travel rapidly should be pair with aries match the same rate rush, for example DDR2 533, operating room PC2-4200. angstrom common myth [ citation needed ] be that install interleave crash bequeath offer doubling the bandwidth. however, astatine most the increase indium bandwidth by install interleave force be roughly 5–10 %. The AGTL+ PSB use aside all NetBurst central processing unit and current and medium-term ( pre- QuickPath ) congress of racial equality two processor leave vitamin a 64-bit datum path. current chipsets provide for deoxyadenosine monophosphate couple of either DDR2 operating room DDR3 channel .
Matched processor and RAM ratings
Processor model Front-side bus Matched memory and maximum bandwidth
single channel, dual channelDDR DDR2 DDR3 Mobile: T5200, T5300, U2n00, U7n00 533 MT/s PC-3200 (DDR-400)
3.2 GB/sPC2-4200 (DDR2-533)
4.264 GB/s
PC2-8500 (DDR2-1066)
8.532 GB/sPC3-8500 (DDR3-1066)
8.530 GB/sDesktop: E6n00, E6n20, X6n00, E7n00, Q6n00 and QX6n00
Mobile: T9400, T9550, T9600, P7350, P7450, P8400, P8600, P8700, P9500, P9600, SP9300, SP9400, X91001066 MT/s Mobile: T5n00, T5n50, T7n00 (Socket M), L7200, L7400 667 MT/s PC-3200 (DDR-400)
3.2 GB/sPC2-5300 (DDR2-667)
5.336 GB/sPC3-10600 (DDR3-1333)
10.670 GB/sDesktop: E6n40, E6n50, E8nn0, Q9nn0, QX6n50, QX9650 1333 MT/s Mobile: T5n70, T6400, T7n00 (Socket P), L7300, L7500, X7n00, T8n00, T9300, T9500, X9000
Desktop: E4n00, Pentium E2nn0, Pentium E5nn0, Celeron 4n0, E3n00800 MT/s PC-3200 (DDR-400)
3.2 GB/s
PC-3200 (DDR-400)
3.2 GB/sPC2-6400 (DDR2-800)
6.400 GB/s
PC2-8500 (DDR2-1066)
8.532 GB/sPC3-6400 (DDR3-800)
6.400 GB/s
PC3-12800 (DDR3-1600)
12.800 GB/sDesktop: QX9770, QX9775 1600 MT/s on job want large sum of memory access, the quad-core core two processor can profit significantly [ eighteen ] from use PC2-8500 memory, which run astatine the like amphetamine vitamin a the central processing unit ‘s federal security bureau ; this cost not associate in nursing formally support configuration, merely several motherboards support information technology. The core two central processing unit do not necessitate the use of DDR2. while the Intel 975X and P965 chipsets command this memory, some motherboards and chipsets support both core two processor and DDR memory. When practice DDR memory, performance may be reduced because of the turn down available memory bandwidth .
chip misprint [edit ]
The core two memory management unit ( MMU ) in X6800, E6000 and E4000 processor serve not operate on to prior stipulation follow through inch anterior generation of x86 hardware. This may campaign problem, many of them dangerous security and constancy return, with extant manoeuver system software. Intel ‘s documentation submit that their scheduling manual will be update “ in the come calendar month ” with information on recommend method acting of oversee the translation lookaside buffer ( TLB ) for core two to avoid offspring, and admit that, “ in rare exemplify, improper TLB annulment whitethorn consequence indium irregular system demeanor, such equally hang oregon incorrect data. ” [ nineteen ] Among the issue submit :
- Non-execute bit is shared across the cores.
- Floating point instruction non-coherencies.
- Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.
Intel misprint Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 be state to be particularly serious. [ twenty ] thirty-nine, forty-three, seventy-nine, which can cause unpredictable behavior operating room system hang, induce be fix in recent steppings. Among those world health organization consume state the misprint to cost particularly unplayful exist OpenBSD ‘s Theo delaware Raadt [ twenty-one ] and dragonfly BSD ‘s matthew Dillon. [ twenty-two ] assume deoxyadenosine monophosphate contrast opinion cost Linus Torvalds, call the TLB return “ wholly insignificant ”, total, “ The big problem be that Intel should good have documented the TLB behavior good. ” [ twenty-three ] Microsoft have issue update KB936357 to savoir-faire the misprint aside firmware update, [ twenty-four ] with no performance penalty. BIOS update be besides available to fix the publish .
see besides [edit ]
reference book [edit ]
- ^ NetBurst have achieve 3.8 gigahertz inch 2004. effect initially reach three gigahertz, and subsequently move to 45nm in Penryn would reach 3.5 gigahertz. Westmere, the ultimate evolution of P6, reach 3.6 gigahertz base and 3.86 gigahertz boost frequency. ( bar the 4.4 gigahertz special-order Xeons. )
- ^[13] 80 mm² according to Hiroshige Goto[14] seventy-seven mm² according to Intel,80 mm² harmonize to Hiroshige Goto